Add initial uarch model

1 files changed, 10 insertions, 0 deletions

diff --git a/isa/isa.h b/isa/isa.h
index 8156c08..4083e16 100644
--- a/isa/isa.h
+++ b/isa/isa.h
@@ -51,6 +51,11 @@ static constexpr std::uint_fast32_t TTO_DATA = 0xff << TTO_DATA_SHIFT;
 static constexpr std::uint_fast32_t TTF_INT_ENABLE = 1 << 0;
 static constexpr std::uint_fast32_t TTF_STATUS_ENABLE = 1 << 1;
 
+static std::string opr_disasm_group1[0377];
+static std::string opr_disasm_group2_pos[0366];
+static std::string opr_disasm_group2_neg[0366];
+static std::string opr_disasm_extended_arith[0376];
+
 struct instruction_context {
     // Known statically at decode time
     bool need_indirect_load = false;    // final_address = mem[init_address]
@@ -67,10 +72,14 @@ struct instruction_context {
     bool need_exec_store = false;       // mem[final_address] = data
     bool possibly_redirects = false;    // %pc = next_pc
 
+    const char *df = nullptr;
+    std::string disasm() const;
+
     std::function<void(instruction_context &ctx)> ef;
     void execute() { ef(*this); }
 
     // May change over the lifetime of the instruction execution
+    unsigned int bits;
     unsigned int next_pc;                       // includes IF
     std::optional<unsigned int> init_address;   // includes DF
     std::optional<unsigned int> final_address;  // includes DF
@@ -81,4 +90,5 @@ struct instruction_context {
     std::optional<unsigned int> mq;
 };
 
+void init_disasm_tables();
 instruction_context decode(std::uint_fast32_t flags, unsigned int pc, unsigned int bits, bool interrupt);