4 files changed, 39 insertions, 21 deletions

diff --git a/isa/checker.cpp b/isa/checker.cpp
index 1919bd1..7bca5c9 100644
--- a/isa/checker.cpp
+++ b/isa/checker.cpp
@@ -4,16 +4,17 @@
 #include "isa/isa.h"
 
 void checker::execute() {
-    assert(!halted);
-    auto int_enable_delay = ctlregs[INT_ENABLE] >> 1;
-    if (ctlregs[INT_ENABLE] & 1) {
-        // check for interrupt
-    }
-    ctlregs[INT_ENABLE] = (int_enable_delay << 1) | int_enable_delay;
+    bool interrupt = system.interact(ctlregs);
+
+    if (ctlregs[HALTED])
+        return;
+
     inst = decode(ctlregs[DATA_INSTRUCTION_FIELD_BUFFER],
                   pc,
-                  mem.fetch(pc));
+                  mem.fetch(pc),
+                  interrupt);
     auto next_pc = inst.next_pc;
+
     if (inst.need_indirect_load) {
         auto addr = mem.fetch(inst.init_address.value());
         if (inst.need_autoinc_store)
@@ -22,8 +23,10 @@ void checker::execute() {
     } else {
         assert(!inst.need_autoinc_store);
     }
+
     if (inst.need_exec_load)
         inst.data = mem.fetch(inst.final_address.value());
+
     if (inst.need_read_acc)
         inst.acc = acc;
     if (inst.need_read_link)
@@ -32,7 +35,9 @@ void checker::execute() {
         inst.mq = mq;
     if (inst.read_ctlreg.has_value())
         inst.ctlval = ctlregs[*inst.read_ctlreg];
+
     inst.execute();
+
     if (inst.need_write_acc)
         acc = inst.acc.value();
     if (inst.need_write_link)
@@ -41,9 +46,10 @@ void checker::execute() {
         mq = inst.mq.value();
     if (inst.write_ctlreg.has_value())
         ctlregs[*inst.write_ctlreg] = inst.ctlval.value();
+
     if (inst.need_exec_store)
         mem.store(inst.final_address.value(), inst.data.value());
+
     assert(inst.next_pc == next_pc || inst.possibly_redirects);
     pc = inst.next_pc;
-    halted = inst.halt;
 }
diff --git a/isa/checker.h b/isa/checker.h
index d70997f..332c483 100644
--- a/isa/checker.h
+++ b/isa/checker.h
@@ -3,6 +3,7 @@
 #include <array>
 #include <map>
 
+#include "io/model.h"
 #include "isa/isa.h"
 
 struct funcmem {
@@ -41,10 +42,11 @@ struct checker {
     unsigned int mq = 0;
     unsigned int pc = 00200;
     std::array<unsigned int, NUM_CTLREGS> ctlregs;
+    iomodel &system;
     instruction_context inst;
-    bool halted = false;
     funcmem mem;
-    checker()
+    checker(iomodel &system)
+        : system(system)
     {
         ctlregs.fill(0);
     }
diff --git a/isa/decode.cpp b/isa/decode.cpp
index 1979982..d24632b 100644
--- a/isa/decode.cpp
+++ b/isa/decode.cpp
@@ -2,15 +2,21 @@
 
 #include "isa/isa.h"
 
-instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bits)
+instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bits, bool interrupt)
 {
-    instruction_context inst;
-
     auto df = dfifb >> 3;
     auto ifb = dfifb & 00007;
 
+    instruction_context inst;
     inst.next_pc = (pc & ~07777) | ((pc + 1) & 07777);
 
+    if (interrupt) {
+        bits = 04000;
+        assert(df == 0);
+        assert(ifb == 0);
+        inst.next_pc = pc;
+    }
+
     switch (bits >> 9) {
         case 0: // AND
             inst.need_exec_load = true;
@@ -121,6 +127,8 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
                 inst.need_read_acc = sma || sza;
                 inst.need_read_link = snl;
                 inst.need_write_acc = cla;
+                if (hlt)
+                    inst.write_ctlreg = HALTED;
                 inst.possibly_redirects = true;
                 inst.ef = [cla, sma, sza, snl, osr, hlt](auto &ctx) {
                     bool skip = false;
@@ -129,7 +137,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
                     if (snl && ctx.link.value()) skip = true;
                     if (cla) ctx.acc = 0;
                     assert(!osr);
-                    if (hlt) ctx.halt = true;
+                    if (hlt) ctx.ctlval = 1;
                     if (skip)
                         ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777);
                 };
@@ -143,6 +151,8 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
                 inst.need_read_acc = spa || sna;
                 inst.need_read_link = szl;
                 inst.need_write_acc = cla;
+                if (hlt)
+                    inst.write_ctlreg = HALTED;
                 inst.possibly_redirects = true;
                 inst.ef = [cla, spa, sna, szl, osr, hlt](auto &ctx) {
                     bool skip = true;
@@ -151,7 +161,7 @@ instruction_context decode(unsigned int dfifb, unsigned int pc, unsigned int bit
                     if (szl && ctx.link.value()) skip = false;
                     if (cla) ctx.acc = 0;
                     assert(!osr);
-                    if (hlt) ctx.halt = true;
+                    if (hlt) ctx.ctlval = 1;
                     if (skip)
                         ctx.next_pc = (ctx.next_pc & 070000) | ((ctx.next_pc + 1) & 007777);
                 };
diff --git a/isa/isa.h b/isa/isa.h
index 11a8db2..bea484e 100644
--- a/isa/isa.h
+++ b/isa/isa.h
@@ -3,19 +3,20 @@
 #include <functional>
 #include <optional>
 
-#include "infra/pipetrace.h"
-
 enum ctlreg {
     DATA_INSTRUCTION_FIELD_BUFFER,  // (df << 3) | if_buffer
     DATA_INSTRUCTION_FIELD_SAVED,   // (df_saved << 3) | if_saved
+    HALTED,
     INT_ENABLE,                     // (int_enable_delay << 1) | int_enable
+    TT_INPUT,                       // (tti_flag << 8) | tti_buffer
+    TT_INPUT_INT_ENABLE,
+    TT_OUTPUT,                      // {tto_flag_old, tto_flag, tto_tx, tto_data}
+    TT_OUTPUT_INT_ENABLE,
 
     NUM_CTLREGS,
 };
 
 struct instruction_context {
-    infra::transaction transaction;
-
     // Known statically at decode time
     bool need_indirect_load = false;    // final_address = mem[init_address]
     bool need_autoinc_store = false;    // mem[init_address] += 1
@@ -43,7 +44,6 @@ struct instruction_context {
     std::optional<unsigned int> acc;
     std::optional<bool> link;
     std::optional<unsigned int> mq;
-    bool halt = false;
 };
 
-instruction_context decode(unsigned int df, unsigned int pc, unsigned int bits);
+instruction_context decode(unsigned int df, unsigned int pc, unsigned int bits, bool interrupt);