1 files changed, 24 insertions, 3 deletions

diff --git a/uarch/core.h b/uarch/core.h
index 0f9be74..a6772f3 100644
--- a/uarch/core.h
+++ b/uarch/core.h
@@ -2,11 +2,14 @@
 
 #include <array>
 
+#include "infra/arbiter.h"
 #include "infra/pipetrace.h"
 #include "infra/port.h"
 #include "io/model.h"
 #include "isa/checker.h"
 #include "isa/isa.h"
+#include "memory/cache.h"
+#include "memory/dram.h"
 
 struct core;
 
@@ -14,7 +17,7 @@ struct fetch_bundle {
     infra::transaction tr;
     unsigned int gen;
     unsigned int pc;
-    unsigned int word;
+    memory::line data;
 };
 
 struct fetch_restart {
@@ -26,9 +29,12 @@ struct fetch_restart {
 struct fetch_stage : public infra::sim {
     core &c;
 
+    memory::inline_cache<8, 2> cache;
+
     unsigned int gen = 0;
     unsigned int pc;
     bool didrestart = false;
+    bool outstandingfill = false;
 
     fetch_stage(core &c);
 
@@ -49,6 +55,7 @@ struct decode_stage : public infra::sim {
     std::array<uint_fast32_t, NUM_CTLREGS> ctlregs;
     std::uint64_t icount;
     instruction_context inst;
+    bool outstandingfill = false;
 
     decode_stage(core &c);
 
@@ -58,11 +65,20 @@ struct decode_stage : public infra::sim {
 struct core {
     iomodel &system;
     funcchecker checker;
-    funcmem mem;
 
+    memory::dram mem{12};
+    infra::port<memory::dram::command> mem_commandp;
+
+    infra::priority_arbiter<memory::dram::command, 2> mem_command_arb;
+
+    infra::port<memory::dram::command> fetch_mem_commandp;
+    infra::port<memory::dram::response> fetch_mem_responsep;
     infra::port<fetch_bundle> fetch_bundlep;
     std::optional<fetch_restart> fetch_restarto;
 
+    infra::port<memory::dram::command> decode_mem_commandp;
+    infra::port<memory::dram::response> decode_mem_responsep;
+
     // Construction order is execution order within a cycle, so this list should be back-to-front (for zero-cycle restarts)
     decode_stage decode{*this};
     fetch_stage fetch{*this};
@@ -70,5 +86,10 @@ struct core {
     core(iomodel &model)
         : system(model)
         , checker(model)
-    { }
+    {
+        mem.commandp = &mem_commandp;
+        mem_command_arb.outp = &mem_commandp;
+        mem_command_arb.peerp[0] = &decode_mem_commandp;
+        mem_command_arb.peerp[1] = &fetch_mem_commandp;
+    }
 };