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authorJulian Blake Kongslie2021-07-06 09:44:36 -0700
committerJulian Blake Kongslie2021-07-06 09:44:36 -0700
commit60e1775b874015a3451e4bde10a8eb30701b1165 (patch)
tree477a2835c0f7e616bdeeabe6aee85f8af8b79650 /sim/memory.sv
downloadbreadboarding-60e1775b874015a3451e4bde10a8eb30701b1165.tar.xz
Initial commit.
Diffstat (limited to 'sim/memory.sv')
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1 files changed, 35 insertions, 0 deletions
diff --git a/sim/memory.sv b/sim/memory.sv
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1module memory
2 #( parameter UROM = "<no file specified>"
3 , parameter UIP_BITS = 15
4 , parameter UROM_BITS = 8
5 , parameter BUS_BITS = 16
6 , parameter IMAGE = "<no file specified>"
7 , parameter BYTE_BITS = 8
8 )
9 ( input bit clk
10 , input bit reset
11 , input bit [UIP_BITS-1:0] uip
12 , inout bit [BUS_BITS-1:0] abus
13 , inout bit [BUS_BITS-1:0] dbus
14 );
15
16bit [BYTE_BITS-1:0] storage [0:(1<<BUS_BITS)-1];
17initial $readmemh(IMAGE, storage);
18
19typedef enum
20 { STORE
21 , OUTDATA
22 } CtrlBit;
23
24bit [UROM_BITS-1:0] ctrl;
25urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
26
27assign dbus = ctrl[OUTDATA] ? {{(BUS_BITS-BYTE_BITS){1'b0}}, storage[abus]} : {(BUS_BITS){1'bZ}};
28
29always @(posedge clk) begin
30 if (ctrl[STORE]) begin
31 storage[abus] <= dbus[BYTE_BITS-1:0];
32 end
33end
34
35endmodule