sim/pc.sv


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module pc
    #(  parameter   UROM        = "<no file specified>"
    ,   parameter   UIP_BITS    = 15
    ,   parameter   UROM_BITS   = 8
    ,   parameter   BUS_BITS    = 16
    ,   parameter   RESET       = 0
    )
    (   input   bit                 clk
    ,   input   bit                 reset
    ,   input   bit [UIP_BITS-1:0]  uip
    ,   inout   bit [BUS_BITS-1:0]  abus
    ,   inout   bit [BUS_BITS-1:0]  dbus
    );

bit [BUS_BITS-1:0] addr;

typedef enum
    { LOAD
    , INCREMENT
    , OUTADDR
    } CtrlBit;

bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);

assign abus = ctrl[OUTADDR] ? addr : {(BUS_BITS){1'bZ}};

always @(posedge clk) begin
    if (reset) begin
        addr <= RESET;
    end else begin
        addr <= (ctrl[LOAD] ? abus : addr) + (ctrl[INCREMENT] ? 1 : 0);
    end
end

endmodule