sim/rf.sv


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module rf
    #(  parameter   UROM        = "<no file specified>"
    ,   parameter   UIP_BITS    = 15
    ,   parameter   UROM_BITS   = 8
    ,   parameter   BUS_BITS    = 16
    ,   parameter   NAME_BITS   = 3
    )
    (   input   bit                 clk
    ,   input   bit                 reset
    ,   input   bit [UIP_BITS-1:0]  uip
    ,   inout   bit [BUS_BITS-1:0]  abus
    ,   inout   bit [BUS_BITS-1:0]  dbus
    );

bit [BUS_BITS-1:0] storage [0:(1<<NAME_BITS)-1];

typedef enum
    { STORE
    , RESET
    , OUTDATA
    } CtrlBit;

bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);

assign dbus = ctrl[OUTDATA] ? storage[abus[NAME_BITS-1:0]] : {(BUS_BITS){1'bZ}};

always @(posedge clk) begin
    if (reset || ctrl[RESET]) begin
        for (int i = 0; i < (1 << NAME_BITS); ++i)
            storage[i] <= 0;
    end else begin
        if (ctrl[STORE]) begin
            storage[abus[NAME_BITS-1:0]] <= dbus;
        end
    end
end

endmodule