sim/tmp.sv


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module tmp
    #(  parameter   UROM        = "<no file specified>"
    ,   parameter   UIP_BITS    = 15
    ,   parameter   UROM_BITS   = 8
    ,   parameter   BUS_BITS    = 16
    )
    (   input   bit                 clk
    ,   input   bit                 reset
    ,   input   bit [UIP_BITS-1:0]  uip
    ,   inout   bit [BUS_BITS-1:0]  abus
    ,   inout   bit [BUS_BITS-1:0]  dbus
    );

bit [BUS_BITS-1:0] x;

typedef enum
    { LOAD
    , LOAD_SEL0
    , OUTADDR
    , OUTDATA
    } CtrlBit;

bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);

bit [0:0] sel;
assign sel = {ctrl[LOAD_SEL0]};

assign abus = ctrl[OUTADDR] ? x : {(BUS_BITS){1'bZ}};
assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};

always @(posedge clk) begin
    if (ctrl[LOAD]) begin
        x <=
            (sel == 0) ? dbus :
            (sel == 1) ? abus :
            {(BUS_BITS){1'bX}};
    end
end

endmodule