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module top
#( parameter UIP_BITS = 15
, parameter UROM_BITS = 8
, parameter BUS_BITS = 16
, parameter MEM_BITS = 8
)
( input bit clk // verilator public
, input bit reset // verilator public
);
bit [UIP_BITS-1:0] uip;
bit [BUS_BITS-1:0] abus;
bit [BUS_BITS-1:0] dbus;
alu #("../out/alu.bin", UIP_BITS, UROM_BITS, BUS_BITS) alu(clk, reset, uip, abus, dbus);
control #("../out/control.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/consts.0.bin", "../out/consts.1.bin", 'h7ff8) control(clk, reset, uip, abus, dbus);
decode #("../out/decode.bin", UIP_BITS, UROM_BITS, BUS_BITS, 12) decode(clk, reset, uip, abus, dbus);
memory #("../out/memory.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/image.hex", MEM_BITS) memory(clk, reset, uip, abus, dbus);
pc #("../out/pc.bin", UIP_BITS, UROM_BITS, BUS_BITS, 0) pc(clk, reset, uip, abus, dbus);
rf #("../out/rf.bin", UIP_BITS, UROM_BITS, BUS_BITS, 3) rf(clk, reset, uip, abus, dbus);
tmp #("../out/tmp0.bin", UIP_BITS, UROM_BITS, BUS_BITS) tmp0(clk, reset, uip, abus, dbus);
tmp #("../out/tmp1.bin", UIP_BITS, UROM_BITS, BUS_BITS) tmp1(clk, reset, uip, abus, dbus);
uart #("../out/uart.bin", UIP_BITS, UROM_BITS, BUS_BITS) uart(clk, reset, uip, abus, dbus);
//always @(negedge clk) $display("pc=%x uip=%x abus=%x dbus=%x tmp0=%x tmp1=%x alu=%x regs=%x:%x:%x:...:%x", pc.addr, uip, abus, dbus, tmp0.x, tmp1.x, alu.x, rf.storage[0], rf.storage[1], rf.storage[2], rf.storage[7]);
endmodule
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