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module uart
#( parameter UROM = "<no file specified>"
, parameter UIP_BITS = 15
, parameter UROM_BITS = 8
, parameter BUS_BITS = 16
)
( input bit clk
, input bit reset
, input bit [UIP_BITS-1:0] uip
, inout bit [BUS_BITS-1:0] abus
, inout bit [BUS_BITS-1:0] dbus
);
bit txfull;
bit rxempty;
assign txfull = 0;
assign rxempty = 0;
typedef enum
{ TX
, RX
, OUTDATA
, OUTDATA_SEL0
} CtrlBit;
bit [UROM_BITS-1:0] ctrl;
urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
bit [0:0] sel;
assign sel = {ctrl[OUTDATA_SEL0]};
bit [BUS_BITS-1:0] dout;
assign dout =
(ctrl[RX]) ? {(BUS_BITS){1'b1}} :
(sel == 0) ? {{(BUS_BITS-1){1'b0}}, txfull} :
(sel == 1) ? {{(BUS_BITS-1){1'b0}}, rxempty} :
{(BUS_BITS){1'bX}};
assign dbus = ctrl[OUTDATA] ? dout : {(BUS_BITS){1'bZ}};
always @(posedge clk) begin
if (ctrl[TX])
$display("tx %x", dbus[7:0]);
end
endmodule
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