Dropping the async interface, and adding some real uarch.

1 files changed, 46 insertions, 0 deletions

diff --git a/uarch/memory.cpp b/uarch/memory.cpp
new file mode 100644
index 0000000..5cf9920
--- /dev/null
+++ b/uarch/memory.cpp
@@ -0,0 +1,46 @@
+#include <algorithm>
+#include <cstdint>
+#include <initializer_list>
+#include <iostream>
+#include <set>
+#include <utility>
+#include <vector>
+
+#include "aisa/aisa.h"
+#include "uarch/memory.h"
+#include "util/assert.h"
+
+namespace uarch {
+
+    MemStage::MemStage(sim::Scheduler &scheduler, sim::Queue<FillReq> &fillreqq, const std::initializer_list<sim::Queue<Fill> *> &fillqs, sim::Queue<Store> &storeq)
+        : sim::Schedulable(scheduler)
+        , fillreqq(fillreqq)
+        , storeq(storeq)
+    {
+        fillreqq.add_reader(this);
+        for (const auto &q : fillqs)
+            q->add_writer(this);
+        storeq.add_reader(this);
+    }
+
+    void MemStage::clock()
+    {
+        if (storeq.available()) {
+            auto s = storeq.read();
+            std::uint64_t x = 0;
+            for (unsigned int i = 0; i < s.bytes.size(); ++i)
+                x |= static_cast<std::uint64_t>(s.bytes[i]) << 8 * i;
+            std::cout << "mem stores " << s.bytes.size() << " bytes to " << s.physical_addr << " <- " << x << "\n";
+            ASSERT(store_mem(s.physical_addr, s.bytes.data(), s.bytes.size()), "Could not complete store");
+        } else if (fillreqq.available()) {
+            auto r = fillreqq.read();
+            std::cout << "mem fills " << r.size << " bytes from " << r.physical_addr << "\n";
+            Fill f;
+            f.physical_addr = r.physical_addr;
+            f.bytes.resize(r.size);
+            ASSERT(fetch_mem(f.bytes.data(), r.physical_addr, r.size), "Could not complete fill");
+            r.fillq->write(std::move(f));
+        }
+    }
+
+}