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authorJulian Blake Kongslie2022-07-02 13:45:09 -0700
committerJulian Blake Kongslie2022-07-02 13:45:09 -0700
commitc72951a36d6cb9775dc1ecd9bc26bc13e796f10c (patch)
tree5a8fe196beba5c7c674d1b3d627c9a0beac849f5 /uarch/memory.h
parentTrivial code reorg. (diff)
downloadissim-c72951a36d6cb9775dc1ecd9bc26bc13e796f10c.tar.xz
Dropping the async interface, and adding some real uarch.
Diffstat (limited to 'uarch/memory.h')
-rw-r--r--uarch/memory.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/uarch/memory.h b/uarch/memory.h
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1#pragma once
2
3#include <initializer_list>
4
5#include "aisa/simple-models.h"
6#include "sim/sim.h"
7#include "sim/queue.h"
8#include "uarch/types.h"
9
10namespace uarch {
11
12 struct MemStage : public sim::Schedulable, aisa::PagedMem<> {
13 sim::Queue<FillReq> &fillreqq;
14 sim::Queue<Store> &storeq;
15
16 MemStage(sim::Scheduler &scheduler, sim::Queue<FillReq> &fillreqq, const std::initializer_list<sim::Queue<Fill> *> &fillqs, sim::Queue<Store> &storeq);
17
18 void clock() override;
19 };
20
21}