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| author | Julian Blake Kongslie | 2022-04-22 22:54:26 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-04-22 22:54:26 -0700 |
| commit | 218fccd59b9750c87907917de245d3b72a518768 (patch) | |
| tree | 4fdfca32b98f215c340154f0af8e8ae40e2b87b1 | |
| parent | Transmit and receive an even parity bit in RS232 uart. (diff) | |
| download | multipdp8-218fccd59b9750c87907917de245d3b72a518768.tar.xz | |
Asynchronous reset on RS232 uart.
| -rw-r--r-- | hdl/rs232.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hdl/rs232.sv b/hdl/rs232.sv index 420f273..9050464 100644 --- a/hdl/rs232.sv +++ b/hdl/rs232.sv | |||
| @@ -25,7 +25,7 @@ module rs232_tx | |||
| 25 | 25 | ||
| 26 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; | 26 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; |
| 27 | 27 | ||
| 28 | always @(posedge clock) begin | 28 | always @(posedge clock, posedge reset) begin |
| 29 | if (reset) begin | 29 | if (reset) begin |
| 30 | out_ready = 0; | 30 | out_ready = 0; |
| 31 | tx = 1; | 31 | tx = 1; |
| @@ -108,7 +108,7 @@ module rs232_rx | |||
| 108 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; | 108 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; |
| 109 | bit parity; | 109 | bit parity; |
| 110 | 110 | ||
| 111 | always @(posedge clock) begin | 111 | always @(posedge clock, posedge reset) begin |
| 112 | if (reset) begin | 112 | if (reset) begin |
| 113 | in_valid = 0; | 113 | in_valid = 0; |
| 114 | state = state.first; | 114 | state = state.first; |