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authorJulian Blake Kongslie2022-06-05 16:23:07 -0700
committerJulian Blake Kongslie2022-06-05 16:23:07 -0700
commit83eb76e0b3f6570b5e27e2295551f648eea96d86 (patch)
treef127b75074a23b4e93f064cddda17da3cef122a2
parentWorking L1 cache. (diff)
downloadmultipdp8-83eb76e0b3f6570b5e27e2295551f648eea96d86.tar.xz
Add cache clearing to the command parser.
-rw-r--r--hdl/command_parser.sv8
-rw-r--r--hdl/mem_cache.sv15
-rw-r--r--hdl/top.sv6
-rwxr-xr-xtool/download.tcl2
4 files changed, 25 insertions, 6 deletions
diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv
index 1520db4..a4a5190 100644
--- a/hdl/command_parser.sv
+++ b/hdl/command_parser.sv
@@ -20,6 +20,8 @@ module command_parser
20 , input bit loop_ready 20 , input bit loop_ready
21 , output bit loop_valid 21 , output bit loop_valid
22 , output bit loop_data 22 , output bit loop_data
23
24 , output bit clear_caches
23 ); 25 );
24 26
25 bit input_byte_valid; 27 bit input_byte_valid;
@@ -43,6 +45,7 @@ module command_parser
43 command_data.mask[i] = ~0; 45 command_data.mask[i] = ~0;
44 command_data.tag = TAG; 46 command_data.tag = TAG;
45 loop_valid = 0; 47 loop_valid = 0;
48 clear_caches = 0;
46 input_byte_valid = 0; 49 input_byte_valid = 0;
47 input_byte = 0; 50 input_byte = 0;
48 loop_count = 0; 51 loop_count = 0;
@@ -62,6 +65,7 @@ module command_parser
62 if (loop_ready && loop_valid) begin 65 if (loop_ready && loop_valid) begin
63 loop_valid = 0; 66 loop_valid = 0;
64 end 67 end
68 clear_caches = 0;
65 69
66 if (!command_valid && !loop_valid) begin 70 if (!command_valid && !loop_valid) begin
67 case (state) 71 case (state)
@@ -106,6 +110,10 @@ module command_parser
106 state = READ_LOOP_COUNT; 110 state = READ_LOOP_COUNT;
107 end 111 end
108 112
113 "$": begin
114 clear_caches = 1;
115 end
116
109 endcase 117 endcase
110 input_byte_valid = 0; 118 input_byte_valid = 0;
111 end 119 end
diff --git a/hdl/mem_cache.sv b/hdl/mem_cache.sv
index 5f3db73..2257a4f 100644
--- a/hdl/mem_cache.sv
+++ b/hdl/mem_cache.sv
@@ -6,6 +6,8 @@ module mem_cache
6 ( input bit clock 6 ( input bit clock
7 , input bit reset 7 , input bit reset
8 8
9 , input bit clear
10
9 , output bit core_command_ready 11 , output bit core_command_ready
10 , input bit core_command_valid 12 , input bit core_command_valid
11 , input pdp_command_t core_command_data 13 , input pdp_command_t core_command_data
@@ -52,16 +54,19 @@ module mem_cache
52 core_response_valid = 0; 54 core_response_valid = 0;
53 outstanding_fill = 0; 55 outstanding_fill = 0;
54 reset_entry = 0; 56 reset_entry = 0;
55 end else if (reset_entry < (1<<SET_BITS)) begin
56 cache[reset_entry] = 0;
57 ++reset_entry;
58 end else begin 57 end else begin
58 if (clear)
59 reset_entry = 0;
60
59 if (ram_command_ready && ram_command_valid) 61 if (ram_command_ready && ram_command_valid)
60 ram_command_valid = 0; 62 ram_command_valid = 0;
61 if (core_response_ready && core_response_valid) 63 if (core_response_ready && core_response_valid)
62 core_response_valid = 0; 64 core_response_valid = 0;
63 65
64 if (ram_response_ready && ram_response_valid) begin 66 if (!outstanding_fill && !reset_entry[SET_BITS]) begin
67 cache[reset_entry[SET_BITS-1:0]] = 0;
68 ++reset_entry;
69 end else if (ram_response_ready && ram_response_valid && outstanding_fill) begin
65 automatic address_tag_t tag; 70 automatic address_tag_t tag;
66 automatic set_t set; 71 automatic set_t set;
67 automatic cache_entry_t entry; 72 automatic cache_entry_t entry;
@@ -100,7 +105,7 @@ module mem_cache
100 end 105 end
101 end 106 end
102 107
103 core_command_ready = !ram_command_valid && !core_response_valid && !outstanding_fill; 108 core_command_ready = reset_entry[SET_BITS] && !ram_command_valid && !core_response_valid && !outstanding_fill;
104 ram_response_ready = !core_response_valid; 109 ram_response_ready = !core_response_valid;
105 end 110 end
106 end 111 end
diff --git a/hdl/top.sv b/hdl/top.sv
index 26006be..5f98ff9 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -234,6 +234,8 @@ module top
234 , .out_data(ram_tx_data) 234 , .out_data(ram_tx_data)
235 ); 235 );
236 236
237 bit clear_caches;
238
237 command_parser parser 239 command_parser parser
238 ( .clock(internal_clock) 240 ( .clock(internal_clock)
239 , .reset(internal_reset) 241 , .reset(internal_reset)
@@ -253,6 +255,8 @@ module top
253 , .loop_ready(loop_ready) 255 , .loop_ready(loop_ready)
254 , .loop_valid(loop_valid) 256 , .loop_valid(loop_valid)
255 , .loop_data(loop_data) 257 , .loop_data(loop_data)
258
259 , .clear_caches(clear_caches)
256 ); 260 );
257 261
258 mem_arbiter memarb 262 mem_arbiter memarb
@@ -491,6 +495,8 @@ module top
491 ( .clock(internal_clock) 495 ( .clock(internal_clock)
492 , .reset(internal_reset) 496 , .reset(internal_reset)
493 497
498 , .clear(clear_caches)
499
494 , .core_command_ready(cache_command_ready) 500 , .core_command_ready(cache_command_ready)
495 , .core_command_valid(cache_command_valid) 501 , .core_command_valid(cache_command_valid)
496 , .core_command_data(cache_command_data) 502 , .core_command_data(cache_command_data)
diff --git a/tool/download.tcl b/tool/download.tcl
index 596e527..45bf5f0 100755
--- a/tool/download.tcl
+++ b/tool/download.tcl
@@ -14,7 +14,7 @@ if {$::argc > 1} {
14 14
15spawn tool/connect 15spawn tool/connect
16 16
17set atline "@[format %x [expr $core * 32768 / $wordsperline]]" 17set atline "\$ @[format %x [expr $core * 32768 / $wordsperline]]"
18send "$atline\n" 18send "$atline\n"
19expect -ex "$atline\r\n" 19expect -ex "$atline\r\n"
20 20