Writeback cache using explicit altsyncram instead of inferred memory.HEADmain

1 files changed, 24 insertions, 0 deletions

diff --git a/PLAN b/PLAN
index e083e8e..60adf5f 100644
--- a/PLAN
+++ b/PLAN
@@ -1,4 +1,28 @@
 0. writeback cache
+    [✔️] Cache dirty bits
+    [✔️] Cache evicting dirty data on fills that would replace
+    [✔️] Cache not immediately forwarding writes
+    [✔️] Fix mem_cache to actually instantiate memory correctly
+        [✔️] Run Quartus in Windows to generate a Verilog template for manual instantiation of RAM blocks
+            [X] Try to use asynchronous clears for reset instead of occupying a port for SETS cycles NOPE
+            [✔️] Need at least one port capable of read-before-write
+            [✔️] Maybe don't need a second port if the first port can make write optional
+        [✔️] We might need to split our accesses across two cycles
+            [X] If so, can we infer the correct logic without explicit instantiation of the megafunction? NOPE
+        [X] Can we do asynchronous clear without explicit instantiation of the megafunction? NOPE
+        [✔️] Copy from said template into mem_cache.sv instead of trying to use inference
+    ---
+    [ ] Arbiter sending snoops to caches in response to CLI writes
+    [ ] Cache updating itself to clean state for write snoops
+    ---
+    [ ] Arbiter sending snoops to caches in response to CLI reads
+    [ ] Arbiter waiting for snoop responses from caches for CLI reads
+    [ ] Arbiter sending correct data for CLI reads (snoop responses in preference over RAM response)
+    [ ] Cache sending snoop responses for read snoops
+    ---
+    [ ] Cache forwarding snoops upstream
+    [ ] Core updating itself for write snoops (no-op)
+    [ ] Core sending snoop responses for read snoops (always no data)
 1. pipelining that works with SMC / start working on minhdl version of the core
 2. write an SPI or I2C master on the FPGA to sample analog inputs
 3. support wider-than-single-word cache lines