Update PLAN.

1 files changed, 10 insertions, 13 deletions

diff --git a/PLAN b/PLAN
index 80701cd..a2bfaaa 100644
--- a/PLAN
+++ b/PLAN
@@ -1,5 +1,13 @@
-1. fix hello.pal (in noncpu)
-2. fix hello.pal (in multipdp8) (it only sees bytes with the lowest bit set)
+1. more scalable memory arbiter
+2. debug rs232 uart
+3. add cts/rts flow control to rs232 uart
+4. rs232-based high speed memory downloader (nios terminal sucks)
+5. add pdp-8 instruction cache
+6. add pdp-8 data cache
+7. add global shared cache
+8. pipelining / start working on minhdl version of the core
+9. ethernet
+∞. fix hello.pal (in noncpu)
 
    Command block:
 
@@ -49,14 +57,3 @@ PDP-8s)+1, so they will wind up being bottlenecks. The memory protocol allows
 arbitrary stalls, so multi-cycle arbitration is possible.
 
 Not shown is the front panel interface.
-
-
-For the front panel:
-
-    We only have enough pins for a single front panel, so we need an arbiter to
-    control which PDP core is talking to the panel.
-
-    Maybe the command parser should have a command for controlling that arbiter?
-
-    Or we could repurpose some of the switches on the panel to control it? The
-    DF and IF switches are sort of an obvious choice here.