diff options
| author | Julian Blake Kongslie | 2022-03-27 16:58:16 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-03-27 16:58:16 -0700 |
| commit | 55d1bc2bc007f48a429ddf556df58d59fdc0f657 (patch) | |
| tree | 3060f65bd592556acdd8873ba9150c295f816643 /altera | |
| parent | Attempt to download for 16 PDP-8s. (diff) | |
| download | multipdp8-55d1bc2bc007f48a429ddf556df58d59fdc0f657.tar.xz | |
Reduce internal clock speed to 30MHz.
Diffstat (limited to '')
| -rw-r--r-- | altera/clocks.sdc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc index c08f897..fd99dad 100644 --- a/altera/clocks.sdc +++ b/altera/clocks.sdc | |||
| @@ -1,3 +1,3 @@ | |||
| 1 | # This is the clock for timing analysis, not timing-driven synthesis. | 1 | # This is the clock for timing analysis, not timing-driven synthesis. |
| 2 | # See init.tcl for the other clock. | 2 | # See init.tcl for the other clock. |
| 3 | create_clock -period "50 MHz" clock | 3 | create_clock -period "30 MHz" clock |