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authorJulian Blake Kongslie2022-05-08 15:51:35 -0700
committerJulian Blake Kongslie2022-05-08 15:51:35 -0700
commit38c5ae5b60eae9562b97da42f47af3861847f8e5 (patch)
tree556fd9e5c38fb2feea56ce5741ca02a5e110ad63 /altera
parentMake the script for setting up the TTY actually connect. (diff)
downloadmultipdp8-38c5ae5b60eae9562b97da42f47af3861847f8e5.tar.xz
*Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.
Diffstat (limited to 'altera')
-rw-r--r--altera/clocks.sdc2
1 files changed, 1 insertions, 1 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index fd99dad..c08f897 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,3 @@
1# This is the clock for timing analysis, not timing-driven synthesis. 1# This is the clock for timing analysis, not timing-driven synthesis.
2# See init.tcl for the other clock. 2# See init.tcl for the other clock.
3create_clock -period "30 MHz" clock 3create_clock -period "50 MHz" clock