Working (but very slow) RS232 UART

1 files changed, 14 insertions, 17 deletions

diff --git a/hdl/core.sv b/hdl/core.sv
index 7fdd20a..6827b8e 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -8,6 +8,14 @@ module core
     (   input   bit clk
     ,   input   bit reset
 
+    ,   input   bit         uart_tx_ready
+    ,   output  bit         uart_tx_valid
+    ,   output  uart_byte_t uart_tx_data
+
+    ,   output  bit         uart_rx_ready
+    ,   input   bit         uart_rx_valid
+    ,   input   uart_byte_t uart_rx_data
+
     ,   input   bit             mem_command_ready
     ,   output  bit             mem_command_valid
     ,   output  pdp_command_t   mem_command
@@ -115,23 +123,12 @@ bit tx_ready;
 bit tx_valid;
 bit [7:0] tx_data;
 
-alt_jtag_atlantic
-    #(  .INSTANCE_ID(JTAG_INSTANCE)
-    ,   .LOG2_RXFIFO_DEPTH(10)
-    ,   .LOG2_TXFIFO_DEPTH(10)
-    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
-    ) uart
-    (   .clk(clk)
-    ,   .rst_n(!reset)
-
-    ,   .r_dat(tx_data)
-    ,   .r_val(tx_valid)
-    ,   .r_ena(tx_ready)
-
-    ,   .t_dat(rx_data)
-    ,   .t_dav(rx_ready)
-    ,   .t_ena(rx_valid)
-    );
+assign tx_ready = uart_tx_ready;
+assign uart_tx_valid = tx_valid;
+assign uart_tx_data = tx_data;
+assign uart_rx_ready = rx_ready;
+assign rx_valid = uart_rx_valid;
+assign rx_data = uart_rx_data;
 
 bit [`PDP_ADDRESS_BITS-3-1:7] page;