diff options
| author | Julian Blake Kongslie | 2022-04-17 15:57:29 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-04-17 15:58:55 -0700 |
| commit | 1bc6bb6857357e3cd2b3756bd9608db86e1fa456 (patch) | |
| tree | 2ddcea2f5b6be3e883a25fd76da493795cd77535 /hdl/rs232.sv | |
| parent | Integrate wrap bits into grey code for FIFO. (diff) | |
| download | multipdp8-1bc6bb6857357e3cd2b3756bd9608db86e1fa456.tar.xz | |
Working (but very slow) RS232 UART
Diffstat (limited to '')
| -rw-r--r-- | hdl/rs232.sv | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/hdl/rs232.sv b/hdl/rs232.sv index 2f631f8..03378ef 100644 --- a/hdl/rs232.sv +++ b/hdl/rs232.sv | |||
| @@ -20,7 +20,7 @@ module rs232_tx | |||
| 20 | , STOP | 20 | , STOP |
| 21 | } state; | 21 | } state; |
| 22 | 22 | ||
| 23 | bit [$clog2(`UART_BYTE_BITS+1):0] data_bits; | 23 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; |
| 24 | 24 | ||
| 25 | always @(posedge clock) begin | 25 | always @(posedge clock) begin |
| 26 | if (reset) begin | 26 | if (reset) begin |
| @@ -34,7 +34,7 @@ module rs232_tx | |||
| 34 | hold_valid = 1; | 34 | hold_valid = 1; |
| 35 | hold = out_data; | 35 | hold = out_data; |
| 36 | state = state.first; | 36 | state = state.first; |
| 37 | data_bits = `UART_BYTE_BITS; | 37 | data_bits = 0; |
| 38 | end | 38 | end |
| 39 | 39 | ||
| 40 | if (hold_valid) begin | 40 | if (hold_valid) begin |
| @@ -46,10 +46,11 @@ module rs232_tx | |||
| 46 | end | 46 | end |
| 47 | 47 | ||
| 48 | DATA: begin | 48 | DATA: begin |
| 49 | --data_bits; | 49 | tx = hold[data_bits]; |
| 50 | tx = !out_data[data_bits]; | 50 | if (data_bits == `UART_BYTE_BITS-1) |
| 51 | if (data_bits == 0) | ||
| 52 | state = state.next; | 51 | state = state.next; |
| 52 | else | ||
| 53 | ++data_bits; | ||
| 53 | end | 54 | end |
| 54 | 55 | ||
| 55 | STOP: begin | 56 | STOP: begin |
| @@ -86,8 +87,8 @@ module rs232_rx | |||
| 86 | , STOP | 87 | , STOP |
| 87 | } state; | 88 | } state; |
| 88 | 89 | ||
| 89 | uart_byte_t buffer; | 90 | uart_byte_t buffer; |
| 90 | bit [$clog2(`UART_BYTE_BITS+1):0] data_bits; | 91 | bit [$clog2(`UART_BYTE_BITS):0] data_bits; |
| 91 | 92 | ||
| 92 | always @(posedge clock) begin | 93 | always @(posedge clock) begin |
| 93 | if (reset) begin | 94 | if (reset) begin |
| @@ -105,21 +106,22 @@ module rs232_rx | |||
| 105 | if (rx == 0) begin | 106 | if (rx == 0) begin |
| 106 | state = state.next; | 107 | state = state.next; |
| 107 | buffer = 0; | 108 | buffer = 0; |
| 108 | data_bits = `UART_BYTE_BITS; | 109 | data_bits = 0; |
| 109 | end | 110 | end |
| 110 | end | 111 | end |
| 111 | 112 | ||
| 112 | DATA: begin | 113 | DATA: begin |
| 113 | --data_bits; | 114 | buffer[data_bits] = rx; |
| 114 | buffer[data_bits] = !rx; | 115 | if (data_bits == `UART_BYTE_BITS-1) |
| 115 | if (data_bits == 0) | ||
| 116 | state = state.next; | 116 | state = state.next; |
| 117 | else | ||
| 118 | ++data_bits; | ||
| 117 | end | 119 | end |
| 118 | 120 | ||
| 119 | STOP: begin | 121 | STOP: begin |
| 120 | if (!in_valid && rx == 1) begin | 122 | if (!in_valid && rx == 1) begin |
| 121 | in_valid = 1; | 123 | in_valid = 1; |
| 122 | in_data = data_bits; | 124 | in_data = buffer; |
| 123 | end | 125 | end |
| 124 | state = state.next; | 126 | state = state.next; |
| 125 | end | 127 | end |