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authorJulian Blake Kongslie2022-05-15 15:53:03 -0700
committerJulian Blake Kongslie2022-05-15 15:53:03 -0700
commit734b6ffb61cf97aeb4e23202ccf9a3027c41e752 (patch)
treebb46b24ab7ba6c04e65735411e872054a8ddef88 /hdl/top.sv
parentOnly phase shift the RS232 tx clock when we are between bytes. (diff)
downloadmultipdp8-734b6ffb61cf97aeb4e23202ccf9a3027c41e752.tar.xz
Change to 1Mbaud RS232
Diffstat (limited to 'hdl/top.sv')
-rw-r--r--hdl/top.sv2
1 files changed, 1 insertions, 1 deletions
diff --git a/hdl/top.sv b/hdl/top.sv
index d7e6acc..76c4d4d 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -101,7 +101,7 @@ module top
101 101
102 rs232_rx 102 rs232_rx
103 #( .PARITY(1) 103 #( .PARITY(1)
104 , .OVERSAMPLE((50_000_000 / 115200)-1) 104 , .OVERSAMPLE((50_000_000 / 1_000_000)-1)
105 ) wirerx 105 ) wirerx
106 ( .clock(rs232_rx_clock) 106 ( .clock(rs232_rx_clock)
107 , .reset(internal_reset) 107 , .reset(internal_reset)