Only phase shift the RS232 tx clock when we are between bytes.

2 files changed, 22 insertions, 1 deletions

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index b898a9c..2a31e31 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -8,6 +8,8 @@ module rs232_tx
     (   input   bit         clock
     ,   input   bit         reset
 
+    ,   output  bit         clock_busy
+
     ,   output  bit         out_ready
     ,   input   bit         out_valid
     ,   input   uart_byte_t out_data
@@ -20,6 +22,8 @@ module rs232_tx
     uart_byte_t hold;
     bit         parity;
 
+    assign      clock_busy = hold_valid;
+
     (* syn_encoding = "one-hot" *) enum int unsigned
         {   START
         ,   DATA
@@ -108,6 +112,7 @@ module rs232_rx
     (   input   bit         clock
     ,   input   bit         reset
 
+    ,   input   bit         clock_busy
     ,   output  bit         clock_out
 
     ,   input   bit         in_ready
@@ -133,6 +138,7 @@ module rs232_rx
 
     bit         [$clog2(OVERSAMPLE+1)+2:0]  sample;
     bit         [$clog2(OVERSAMPLE+1):0]    clock_counter;
+    bit         [$clog2(OVERSAMPLE+1):0]    next_clock_counter;
 
     always @(posedge clock, posedge reset) begin
         if (reset) begin
@@ -145,6 +151,7 @@ module rs232_rx
             parity = PARITY;
             sample = 0;
             clock_counter = 0;
+            next_clock_counter = 0;
         end else begin
             automatic bit ok = 0;
 
@@ -170,6 +177,15 @@ module rs232_rx
                 clock_out = 0;
             end
 
+            ++next_clock_counter;
+            if (next_clock_counter > OVERSAMPLE) begin
+                next_clock_counter = 0;
+                if (!clock_busy) begin
+                    clock_out = 1;
+                    clock_counter = 0;
+                end
+            end
+
             if (ok) begin
                 case (state)
 
@@ -208,7 +224,7 @@ module rs232_rx
                             in_data = buffer;
                         end
                         if (txd == 1 && parity == 0) begin
-                            clock_counter = (OVERSAMPLE+1)/2;
+                            next_clock_counter = (OVERSAMPLE+1)/2;
                         end
                         if (txd == 1)
                             state = state.first;
diff --git a/hdl/top.sv b/hdl/top.sv
index 2ee6be9..d7e6acc 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -52,6 +52,8 @@ module top
     bit rs232_rx_clock;
     assign rs232_rx_clock = internal_clock;
 
+    bit rs232_clock_busy;
+
     bit         wire_tx_ready;
     bit         wire_tx_valid;
     uart_byte_t wire_tx_data;
@@ -63,6 +65,8 @@ module top
         (   .clock(rs232_tx_clock)
         ,   .reset(rs232_tx_reset)
 
+        ,   .clock_busy(rs232_clock_busy)
+
         ,   .out_ready(wire_tx_ready)
         ,   .out_valid(wire_tx_valid)
         ,   .out_data(wire_tx_data)
@@ -102,6 +106,7 @@ module top
         (   .clock(rs232_rx_clock)
         ,   .reset(internal_reset)
 
+        ,   .clock_busy(rs232_clock_busy)
         ,   .clock_out(rs232_tx_clock)
 
         ,   .in_ready(wire_rx_ready)