First pass at RS232 tx/rx modules.

1 files changed, 131 insertions, 0 deletions

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
new file mode 100644
index 0000000..2f631f8
--- /dev/null
+++ b/hdl/rs232.sv
@@ -0,0 +1,131 @@
+`include "defs.svh"
+
+module rs232_tx
+    (   input   bit         clock
+    ,   input   bit         reset
+
+    ,   output  bit         out_ready
+    ,   input   bit         out_valid
+    ,   input   uart_byte_t out_data
+
+    ,   output  bit         tx
+    );
+
+    bit         hold_valid;
+    uart_byte_t hold;
+
+    (* syn_encoding = "one-hot" *) enum int unsigned
+        {   START
+        ,   DATA
+        ,   STOP
+        } state;
+
+    bit [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+
+    always @(posedge clock) begin
+        if (reset) begin
+            out_ready = 0;
+            tx = 1;
+            hold_valid = 0;
+            state = state.first;
+            data_bits = 0;
+        end else begin
+            if (out_ready && out_valid) begin
+                hold_valid = 1;
+                hold = out_data;
+                state = state.first;
+                data_bits = `UART_BYTE_BITS;
+            end
+
+            if (hold_valid) begin
+                case (state)
+
+                    START: begin
+                        tx = 0;
+                        state = state.next;
+                    end
+
+                    DATA: begin
+                        --data_bits;
+                        tx = !out_data[data_bits];
+                        if (data_bits == 0)
+                            state = state.next;
+                    end
+
+                    STOP: begin
+                        hold_valid = 0;
+                        tx = 1;
+                        state = state.next;
+                    end
+
+                endcase
+            end else begin
+                tx = 1;
+            end
+
+            out_ready = !hold_valid;
+        end
+    end
+
+endmodule
+
+module rs232_rx
+    (   input   bit         clock
+    ,   input   bit         reset
+
+    ,   input   bit         in_ready
+    ,   output  bit         in_valid
+    ,   output  uart_byte_t in_data
+
+    ,   input   bit         rx
+    );
+
+    (* syn_encoding = "one-hot" *) enum int unsigned
+        {   START
+        ,   DATA
+        ,   STOP
+        } state;
+
+    uart_byte_t                                 buffer;
+    bit         [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+
+    always @(posedge clock) begin
+        if (reset) begin
+            in_valid = 0;
+            state = state.first;
+            buffer = 0;
+            data_bits = 0;
+        end else begin
+            if (in_ready && in_valid)
+                in_valid = 0;
+
+            case (state)
+
+                START: begin
+                    if (rx == 0) begin
+                        state = state.next;
+                        buffer = 0;
+                        data_bits = `UART_BYTE_BITS;
+                    end
+                end
+
+                DATA: begin
+                    --data_bits;
+                    buffer[data_bits] = !rx;
+                    if (data_bits == 0)
+                        state = state.next;
+                end
+
+                STOP: begin
+                    if (!in_valid && rx == 1) begin
+                        in_valid = 1;
+                        in_data = data_bits;
+                    end
+                    state = state.next;
+                end
+
+            endcase
+        end
+    end
+
+endmodule