Fix DRAM timings to avoid back-to-back transactions.

1 files changed, 11 insertions, 3 deletions

diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 6eeb46d..8922a09 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -1,5 +1,8 @@
 `include "defs.svh"
 
+`define RESET_CYCLES    5   // Spec wants 100ns
+`define TRWR_CYCLES     2   // Spec wants 40ns
+
 module ram_controller
     (   input   bit                 clock
     ,   input   bit                 reset
@@ -82,7 +85,8 @@ module ram_controller
         ,   TOGGLE_CLOCK
         } half_state;
 
-    bit [2:0]   reset_counter;
+    bit [$clog2(`RESET_CYCLES+1):0] reset_counter;
+    bit [$clog2(`TRWR_CYCLES+1):0]  trwr_counter;
 
     bit         prev_rwds;
 
@@ -100,10 +104,11 @@ module ram_controller
             base_address = 0;
             slow = 0;
             word_count = `RAM_LINE_WORDS;
+            trwr_counter = `TRWR_CYCLES;
             state = state.first;
             half_state = half_state.first;
             if (reset)
-                reset_counter = 5; // Spec wants >= 100ns of reset
+                reset_counter = `RESET_CYCLES; // Spec wants >= 100ns of reset
             else
                 reset_counter = reset_counter - 1;
         end else begin
@@ -119,11 +124,12 @@ module ram_controller
                 state = state.first;
             end
 
-            if (!valid) begin
+            if (!valid || trwr_counter != 0) begin
                 ram_rwds_oe = 0;
                 ram_data_oe = 0;
                 ram_csn = 1;
                 ram_clkp = 0;
+                if (trwr_counter != 0) --trwr_counter;
             end else if (half_state == TOGGLE_CLOCK) begin
                 half_state = half_state.next;
                 if (state != CHIP_SELECT && state != SEND_COMMAND_1)
@@ -217,6 +223,7 @@ module ram_controller
                 end
 
                 endcase
+
                 if (!stall) begin
                     state = state.next;
                     if (state == state.first) begin
@@ -228,6 +235,7 @@ module ram_controller
                             result_data.data = command.data;
                             result_data.tag = command.tag;
                         end
+                        trwr_counter = `TRWR_CYCLES;
                     end
                 end
             end