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| author | Julian Blake Kongslie | 2022-06-05 15:34:23 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-06-05 15:42:26 -0700 |
| commit | 9ce65b7d3573d92e1d98a13b58a5d5763ba073c5 (patch) | |
| tree | 7486552ff9428dcb76e22593f445a657b121f443 /tcl | |
| parent | SMC micro. (diff) | |
| download | multipdp8-9ce65b7d3573d92e1d98a13b58a5d5763ba073c5.tar.xz | |
Working L1 cache.
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/init.tcl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl index 9c94592..4e4660d 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -5,6 +5,7 @@ set_global_assignment -name DEVICE 10CL025YU256I7G | |||
| 5 | set_global_assignment -name TOP_LEVEL_ENTITY top | 5 | set_global_assignment -name TOP_LEVEL_ENTITY top |
| 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 | 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 |
| 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" | 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" |
| 8 | #set_global_assignment -name VERILOG_MACRO "NO_L1_CACHE=1" | ||
| 8 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 1 | 9 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 1 |
| 9 | set_global_assignment -name ENABLE_SIGNALTAP OFF | 10 | set_global_assignment -name ENABLE_SIGNALTAP OFF |
| 10 | 11 | ||