2 files changed, 37 insertions, 37 deletions
diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 2949201..b898a9c 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -3,7 +3,7 @@
 module rs232_tx
    #(  PARITY      = 0
    ,   STOP_BITS   = 2
-    ,   CTS_BITS    = 3
+    ,   RTS_BITS    = 3
    )
    (   input   bit         clock
    ,   input   bit         reset
@@ -12,8 +12,8 @@ module rs232_tx
    ,   input   bit         out_valid
    ,   input   uart_byte_t out_data
-    ,   output  bit         tx
+    ,   output  bit         rxd
-    ,   input   bit         cts
+    ,   input   bit         rts
    );
    bit         hold_valid;
@@ -30,18 +30,18 @@ module rs232_tx
    bit [$clog2($bits(uart_byte_t)):0]  data_bits;
    bit [$clog2(STOP_BITS):0]           stop_bits;
-    bit [CTS_BITS-1:0]    cts_samples;
+    bit [RTS_BITS-1:0]    rts_samples;
    always @(posedge clock, posedge reset) begin
        if (reset) begin
            out_ready = 0;
-            tx = 1;
+            rxd = 1;
            hold_valid = 0;
            parity = PARITY;
            state = state.first;
            data_bits = 0;
            stop_bits = 0;
-            cts_samples = 0;
+            rts_samples = 0;
        end else begin
            if (out_ready && out_valid) begin
                hold_valid = 1;
@@ -52,23 +52,23 @@ module rs232_tx
                stop_bits = 0;
            end
-            cts_samples = cts_samples << 1;
+            rts_samples = rts_samples << 1;
-            cts_samples[0] = cts;
+            rts_samples[0] = rts;
            if (hold_valid) begin
                case (state)
                    START: begin
-                        if (cts_samples == 0) begin
+                        if (rts_samples == 0) begin
-                            tx = 0;
+                            rxd = 0;
                            state = state.next;
                        end
                    end
                    DATA: begin
-                        tx = hold[0];
+                        rxd = hold[0];
                        hold = hold >> 1;
-                        parity = parity ^ tx;
+                        parity = parity ^ rxd;
                        if (data_bits == `UART_BYTE_BITS-1)
                            state = state.next;
                        else
@@ -76,12 +76,12 @@ module rs232_tx
                    end
                    PARITY_BIT: begin
-                        tx = parity;
+                        rxd = parity;
                        state = state.next;
                    end
                    STOP: begin
-                        tx = 1;
+                        rxd = 1;
                        if (stop_bits == STOP_BITS-1) begin
                            hold_valid = 0;
                            state = state.next;
@@ -92,7 +92,7 @@ module rs232_tx
                endcase
            end else begin
-                tx = 1;
+                rxd = 1;
            end
            out_ready = !hold_valid;
@@ -114,8 +114,8 @@ module rs232_rx
    ,   output  bit         in_valid
    ,   output  uart_byte_t in_data
-    ,   input   bit         rx
+    ,   input   bit         txd
-    ,   output  bit         rts
+    ,   output  bit         cts
    );
    (* syn_encoding = "one-hot" *) enum int unsigned
@@ -138,7 +138,7 @@ module rs232_rx
        if (reset) begin
            clock_out = 0;
            in_valid = 0;
-            rts = 1;
+            cts = 1;
            state = state.first;
            buffer = 0;
            data_bits = 0;
@@ -174,7 +174,7 @@ module rs232_rx
                case (state)
                    START: begin
-                        if (rx == 0) begin
+                        if (txd == 0) begin
                            state = state.next;
                            if (OVERSAMPLE == 0)
                                state = state.next;
@@ -189,8 +189,8 @@ module rs232_rx
                    DATA: begin
                        buffer = buffer >> 1;
-                        buffer[`UART_BYTE_BITS-1] = rx;
+                        buffer[`UART_BYTE_BITS-1] = txd;
-                        parity = parity ^ rx;
+                        parity = parity ^ txd;
                        if (data_bits == `UART_BYTE_BITS-1)
                            state = state.next;
                        else
@@ -198,33 +198,33 @@ module rs232_rx
                    end
                    PARITY_BIT: begin
-                        parity = parity ^ rx;
+                        parity = parity ^ txd;
                        state = state.next;
                    end
                    STOP: begin
-                        if (!in_valid && rx == 1 && parity == 0) begin
+                        if (!in_valid && txd == 1 && parity == 0) begin
                            in_valid = 1;
                            in_data = buffer;
                        end
-                        if (rx == 1 && parity == 0) begin
+                        if (txd == 1 && parity == 0) begin
                            clock_counter = (OVERSAMPLE+1)/2;
                        end
-                        if (rx == 1)
+                        if (txd == 1)
                            state = state.first;
                        else
                            state = state.next;
                    end
                    REALSTOP: begin
-                        if (rx == 1)
+                        if (txd == 1)
                            state = state.first;
                    end
                endcase
            end
-            rts = !(state == state.first && !in_valid);
+            cts = !(state == state.first && !in_valid);
        end
    end
diff --git a/hdl/top.sv b/hdl/top.sv
index a58ff0e..2ee6be9 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -8,10 +8,10 @@ module top
    ,   inout   wire    [28:13] gpiob
    ,   inout   wire    [40:31] gpioc
-    ,   output  wire            rs232_tx
+    ,   output  wire            rs232_rxd
-    ,   input   wire            rs232_rx
+    ,   input   wire            rs232_txd
-    ,   output  wire            rs232_rts
+    ,   output  wire            rs232_cts
-    ,   input   wire            rs232_cts
+    ,   input   wire            rs232_rts
    ,   output  wire            debug_tx
    ,   output  wire            debug_rx
@@ -24,8 +24,8 @@ module top
    ,   inout   bit     [7:0]   ram_data
    );
-    assign debug_tx = rs232_tx;
+    assign debug_tx = rs232_rxd;
-    assign debug_rx = rs232_rx;
+    assign debug_rx = rs232_txd;
    bit internal_clock;
    bit internal_reset;
@@ -67,8 +67,8 @@ module top
        ,   .out_valid(wire_tx_valid)
        ,   .out_data(wire_tx_data)
-        ,   .tx(rs232_tx)
+        ,   .rxd(rs232_rxd)
-        ,   .cts(rs232_cts)
+        ,   .rts(rs232_rts)
        );
    bit         rs232_tx_ready;
@@ -108,8 +108,8 @@ module top
        ,   .in_valid(wire_rx_valid)
        ,   .in_data(wire_rx_data)
-        ,   .rx(rs232_rx)
+        ,   .txd(rs232_txd)
-        ,   .rts(rs232_rts)
+        ,   .cts(rs232_cts)
        );
    bit         rs232_rx_ready;

diff --git a/hdl/rs232.sv b/hdl/rs232.sv index 2949201..b898a9c 100644 --- a/hdl/rs232.sv +++ b/hdl/rs232.sv
@@ -3,7 +3,7 @@
3	module rs232_tx	3	module rs232_tx
4	#( PARITY = 0	4	#( PARITY = 0
5	, STOP_BITS = 2	5	, STOP_BITS = 2
6	, CTS_BITS = 3	6	, RTS_BITS = 3
7	)	7	)
8	( input bit clock	8	( input bit clock
9	, input bit reset	9	, input bit reset
@@ -12,8 +12,8 @@ module rs232_tx
12	, input bit out_valid	12	, input bit out_valid
13	, input uart_byte_t out_data	13	, input uart_byte_t out_data
14		14
15	, output bit tx	15	, output bit rxd
16	, input bit cts	16	, input bit rts
17	);	17	);
18		18
19	bit hold_valid;	19	bit hold_valid;
@@ -30,18 +30,18 @@ module rs232_tx
30	bit [$clog2($bits(uart_byte_t)):0] data_bits;	30	bit [$clog2($bits(uart_byte_t)):0] data_bits;
31	bit [$clog2(STOP_BITS):0] stop_bits;	31	bit [$clog2(STOP_BITS):0] stop_bits;
32		32
33	bit [CTS_BITS-1:0] cts_samples;	33	bit [RTS_BITS-1:0] rts_samples;
34		34
35	always @(posedge clock, posedge reset) begin	35	always @(posedge clock, posedge reset) begin
36	if (reset) begin	36	if (reset) begin
37	out_ready = 0;	37	out_ready = 0;
38	tx = 1;	38	rxd = 1;
39	hold_valid = 0;	39	hold_valid = 0;
40	parity = PARITY;	40	parity = PARITY;
41	state = state.first;	41	state = state.first;
42	data_bits = 0;	42	data_bits = 0;
43	stop_bits = 0;	43	stop_bits = 0;
44	cts_samples = 0;	44	rts_samples = 0;
45	end else begin	45	end else begin
46	if (out_ready && out_valid) begin	46	if (out_ready && out_valid) begin
47	hold_valid = 1;	47	hold_valid = 1;
@@ -52,23 +52,23 @@ module rs232_tx
52	stop_bits = 0;	52	stop_bits = 0;
53	end	53	end
54		54
55	cts_samples = cts_samples << 1;	55	rts_samples = rts_samples << 1;
56	cts_samples[0] = cts;	56	rts_samples[0] = rts;
57		57
58	if (hold_valid) begin	58	if (hold_valid) begin
59	case (state)	59	case (state)
60		60
61	START: begin	61	START: begin
62	if (cts_samples == 0) begin	62	if (rts_samples == 0) begin
63	tx = 0;	63	rxd = 0;
64	state = state.next;	64	state = state.next;
65	end	65	end
66	end	66	end
67		67
68	DATA: begin	68	DATA: begin
69	tx = hold[0];	69	rxd = hold[0];
70	hold = hold >> 1;	70	hold = hold >> 1;
71	parity = parity ^ tx;	71	parity = parity ^ rxd;
72	if (data_bits == `UART_BYTE_BITS-1)	72	if (data_bits == `UART_BYTE_BITS-1)
73	state = state.next;	73	state = state.next;
74	else	74	else
@@ -76,12 +76,12 @@ module rs232_tx
76	end	76	end
77		77
78	PARITY_BIT: begin	78	PARITY_BIT: begin
79	tx = parity;	79	rxd = parity;
80	state = state.next;	80	state = state.next;
81	end	81	end
82		82
83	STOP: begin	83	STOP: begin
84	tx = 1;	84	rxd = 1;
85	if (stop_bits == STOP_BITS-1) begin	85	if (stop_bits == STOP_BITS-1) begin
86	hold_valid = 0;	86	hold_valid = 0;
87	state = state.next;	87	state = state.next;
@@ -92,7 +92,7 @@ module rs232_tx
92		92
93	endcase	93	endcase
94	end else begin	94	end else begin
95	tx = 1;	95	rxd = 1;
96	end	96	end
97		97
98	out_ready = !hold_valid;	98	out_ready = !hold_valid;
@@ -114,8 +114,8 @@ module rs232_rx
114	, output bit in_valid	114	, output bit in_valid
115	, output uart_byte_t in_data	115	, output uart_byte_t in_data
116		116
117	, input bit rx	117	, input bit txd
118	, output bit rts	118	, output bit cts
119	);	119	);
120		120
121	(* syn_encoding = "one-hot" *) enum int unsigned	121	(* syn_encoding = "one-hot" *) enum int unsigned
@@ -138,7 +138,7 @@ module rs232_rx
138	if (reset) begin	138	if (reset) begin
139	clock_out = 0;	139	clock_out = 0;
140	in_valid = 0;	140	in_valid = 0;
141	rts = 1;	141	cts = 1;
142	state = state.first;	142	state = state.first;
143	buffer = 0;	143	buffer = 0;
144	data_bits = 0;	144	data_bits = 0;
@@ -174,7 +174,7 @@ module rs232_rx
174	case (state)	174	case (state)
175		175
176	START: begin	176	START: begin
177	if (rx == 0) begin	177	if (txd == 0) begin
178	state = state.next;	178	state = state.next;
179	if (OVERSAMPLE == 0)	179	if (OVERSAMPLE == 0)
180	state = state.next;	180	state = state.next;
@@ -189,8 +189,8 @@ module rs232_rx
189		189
190	DATA: begin	190	DATA: begin
191	buffer = buffer >> 1;	191	buffer = buffer >> 1;
192	buffer[`UART_BYTE_BITS-1] = rx;	192	buffer[`UART_BYTE_BITS-1] = txd;
193	parity = parity ^ rx;	193	parity = parity ^ txd;
194	if (data_bits == `UART_BYTE_BITS-1)	194	if (data_bits == `UART_BYTE_BITS-1)
195	state = state.next;	195	state = state.next;
196	else	196	else
@@ -198,33 +198,33 @@ module rs232_rx
198	end	198	end
199		199
200	PARITY_BIT: begin	200	PARITY_BIT: begin
201	parity = parity ^ rx;	201	parity = parity ^ txd;
202	state = state.next;	202	state = state.next;
203	end	203	end
204		204
205	STOP: begin	205	STOP: begin
206	if (!in_valid && rx == 1 && parity == 0) begin	206	if (!in_valid && txd == 1 && parity == 0) begin
207	in_valid = 1;	207	in_valid = 1;
208	in_data = buffer;	208	in_data = buffer;
209	end	209	end
210	if (rx == 1 && parity == 0) begin	210	if (txd == 1 && parity == 0) begin
211	clock_counter = (OVERSAMPLE+1)/2;	211	clock_counter = (OVERSAMPLE+1)/2;
212	end	212	end
213	if (rx == 1)	213	if (txd == 1)
214	state = state.first;	214	state = state.first;
215	else	215	else
216	state = state.next;	216	state = state.next;
217	end	217	end
218		218
219	REALSTOP: begin	219	REALSTOP: begin
220	if (rx == 1)	220	if (txd == 1)
221	state = state.first;	221	state = state.first;
222	end	222	end
223		223
224	endcase	224	endcase
225	end	225	end
226		226
227	rts = !(state == state.first && !in_valid);	227	cts = !(state == state.first && !in_valid);
228	end	228	end
229	end	229	end
230		230


diff --git a/hdl/top.sv b/hdl/top.sv index a58ff0e..2ee6be9 100644 --- a/hdl/top.sv +++ b/hdl/top.sv
@@ -8,10 +8,10 @@ module top
8	, inout wire [28:13] gpiob	8	, inout wire [28:13] gpiob
9	, inout wire [40:31] gpioc	9	, inout wire [40:31] gpioc
10		10
11	, output wire rs232_tx	11	, output wire rs232_rxd
12	, input wire rs232_rx	12	, input wire rs232_txd
13	, output wire rs232_rts	13	, output wire rs232_cts
14	, input wire rs232_cts	14	, input wire rs232_rts
15		15
16	, output wire debug_tx	16	, output wire debug_tx
17	, output wire debug_rx	17	, output wire debug_rx
@@ -24,8 +24,8 @@ module top
24	, inout bit [7:0] ram_data	24	, inout bit [7:0] ram_data
25	);	25	);
26		26
27	assign debug_tx = rs232_tx;	27	assign debug_tx = rs232_rxd;
28	assign debug_rx = rs232_rx;	28	assign debug_rx = rs232_txd;
29		29
30	bit internal_clock;	30	bit internal_clock;
31	bit internal_reset;	31	bit internal_reset;
@@ -67,8 +67,8 @@ module top
67	, .out_valid(wire_tx_valid)	67	, .out_valid(wire_tx_valid)
68	, .out_data(wire_tx_data)	68	, .out_data(wire_tx_data)
69		69
70	, .tx(rs232_tx)	70	, .rxd(rs232_rxd)
71	, .cts(rs232_cts)	71	, .rts(rs232_rts)
72	);	72	);
73		73
74	bit rs232_tx_ready;	74	bit rs232_tx_ready;
@@ -108,8 +108,8 @@ module top
108	, .in_valid(wire_rx_valid)	108	, .in_valid(wire_rx_valid)
109	, .in_data(wire_rx_data)	109	, .in_data(wire_rx_data)
110		110
111	, .rx(rs232_rx)	111	, .txd(rs232_txd)
112	, .rts(rs232_rts)	112	, .cts(rs232_cts)
113	);	113	);
114		114
115	bit rs232_rx_ready;	115	bit rs232_rx_ready;