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* Transmit two stop bits to RS232 uart.Julian Blake Kongslie2022-04-221-2/+8
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* Refer to wrap bits instead of previous greycode in FIFO greycode calculation.Julian Blake Kongslie2022-04-171-2/+2
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* Fix whitespace/maxlinesize handling in p8bin2uart.Julian Blake Kongslie2022-04-171-8/+7
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* Working (but very slow) RS232 UARTJulian Blake Kongslie2022-04-175-35/+165
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* Integrate wrap bits into grey code for FIFO.Julian Blake Kongslie2022-03-281-5/+8
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* Update PLAN.Julian Blake Kongslie2022-03-271-13/+10
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* 12 PDP-8s! :-)Julian Blake Kongslie2022-03-271-1/+1
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* A more-fair memory arbiter that actually works.Julian Blake Kongslie2022-03-271-31/+34
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* Add RX/TX/RTS/CTS pin assignments for future RS232 work.Julian Blake Kongslie2022-03-271-0/+5
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* Use the DF and IF switches as a selector for which PDP-8 owns the panel.Julian Blake Kongslie2022-03-271-89/+92
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* Add a clock output pin for debugging the PLL.Julian Blake Kongslie2022-03-272-0/+5
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* Attempt to make somewhat less error-prone downloads.Julian Blake Kongslie2022-03-272-6/+5
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* Reduce internal clock speed to 30MHz.Julian Blake Kongslie2022-03-272-3/+3
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* Attempt to download for 16 PDP-8s.Julian Blake Kongslie2022-03-271-8/+16
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* Don't use SystemVerilog parametric types because Altera doesn't support them.Julian Blake Kongslie2022-03-271-9/+9
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* First pass at RS232 tx/rx modules.Julian Blake Kongslie2022-03-271-0/+131
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* Add basic clock-domain-crossing FIFO.Julian Blake Kongslie2022-03-261-0/+68
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* Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~Julian Blake Kongslie2022-03-203-48/+127
| | | | | | It looks like we could probably fit 16 on the current FPGA, just about. (doesn't meet timing at 50MHz, should in theory work at 40MHz)
* Cleanup of PDP-8 core to support arbitrated memory protocol.Julian Blake Kongslie2022-03-201-190/+109
| | | | No support yet for multiple words per line; otherwise complete.
* Support loading RIMs and multi-word lines via the UART loader.Julian Blake Kongslie2022-03-202-12/+24
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* Add a few useful memory images.Julian Blake Kongslie2022-03-205-4141/+0
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* Temporary change to PDP-8 internal memory to match controller protocolJulian Blake Kongslie2022-03-201-57/+86
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* Clean up p8bin2uart and support dumping multiple words per line.Julian Blake Kongslie2022-03-181-27/+73
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* Redraw the diagram in PLAN to make it a little prettier.Julian Blake Kongslie2022-03-181-23/+46
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* Minor paranoia about ensuring that we're in the correct half_stateJulian Blake Kongslie2022-03-181-0/+1
| | | | coming out of t_rwr delay between memory transactions
* Ignore colons on inputs; use them to separate words in output.Julian Blake Kongslie2022-03-182-7/+19
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* Trivial change to make it a little easier to understand the mem arbiter.Julian Blake Kongslie2022-03-181-1/+1
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* Add a few notes.Julian Blake Kongslie2022-03-131-0/+12
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* Import p8bin2* tools into repo.Julian Blake Kongslie2022-03-132-0/+334
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* Change command parser to support bulk download script.Julian Blake Kongslie2022-03-132-23/+118
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* Add memory arbiter and broadcast in between command UART and DRAM.Julian Blake Kongslie2022-03-133-17/+203
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* Fix DRAM timings to avoid back-to-back transactions.Julian Blake Kongslie2022-03-131-3/+11
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* Change FIFO size for UARTs to 1024 bytes in each direction.Julian Blake Kongslie2022-03-132-4/+4
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* Print a newline after memory read result prints.Julian Blake Kongslie2022-03-131-26/+32
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* Adding packed keyword to structs and tweaking tag_t slightly.Julian Blake Kongslie2022-03-131-7/+7
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* Reformat PLAN to be a little prettier.Julian Blake Kongslie2022-03-131-17/+24
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* Switch back to focal69 instead of broken hello.pal.Julian Blake Kongslie2022-03-011-2/+1
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* Don't use the bottom data bit as the ready signal :-DJulian Blake Kongslie2022-02-281-1/+1
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* Initial commit.Julian Blake Kongslie2022-02-2718-0/+6361