diff options
| author | Julian Blake Kongslie | 2022-03-27 16:58:16 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-03-27 16:58:16 -0700 |
| commit | 55d1bc2bc007f48a429ddf556df58d59fdc0f657 (patch) | |
| tree | 3060f65bd592556acdd8873ba9150c295f816643 | |
| parent | Attempt to download for 16 PDP-8s. (diff) | |
| download | multipdp8-55d1bc2bc007f48a429ddf556df58d59fdc0f657.tar.xz | |
Reduce internal clock speed to 30MHz.
| -rw-r--r-- | altera/clocks.sdc | 2 | ||||
| -rw-r--r-- | hdl/top.sv | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc index c08f897..fd99dad 100644 --- a/altera/clocks.sdc +++ b/altera/clocks.sdc | |||
| @@ -1,3 +1,3 @@ | |||
| 1 | # This is the clock for timing analysis, not timing-driven synthesis. | 1 | # This is the clock for timing analysis, not timing-driven synthesis. |
| 2 | # See init.tcl for the other clock. | 2 | # See init.tcl for the other clock. |
| 3 | create_clock -period "50 MHz" clock | 3 | create_clock -period "30 MHz" clock |
| @@ -19,8 +19,8 @@ module top | |||
| 19 | bit internal_clock; | 19 | bit internal_clock; |
| 20 | bit internal_reset; | 20 | bit internal_reset; |
| 21 | pll | 21 | pll |
| 22 | #( .MULTIPLY_BY(1) | 22 | #( .MULTIPLY_BY(3) |
| 23 | , .DIVIDE_BY(1) | 23 | , .DIVIDE_BY(5) |
| 24 | ) fastpll | 24 | ) fastpll |
| 25 | ( .native_clk(clock) | 25 | ( .native_clk(clock) |
| 26 | , .reset_n(resetn) | 26 | , .reset_n(resetn) |