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* Fix the RS232 receive state machine 😠💢:mad:Julian Blake Kongslie2022-05-151-1/+1
* Only phase shift the RS232 tx clock when we are between bytes.Julian Blake Kongslie2022-05-151-1/+17
* Consistent RS232 wire names (DCE side names is used everywhere)Julian Blake Kongslie2022-05-151-27/+27
* Demand that CTS is asserted for multiple symbol periods before transmit.Julian Blake Kongslie2022-05-081-1/+8
* *Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.Julian Blake Kongslie2022-05-081-33/+76
* Oversample RS232 RX uart.Julian Blake Kongslie2022-04-221-30/+49
* Asynchronous reset on RS232 uart.Julian Blake Kongslie2022-04-221-2/+2
* Transmit and receive an even parity bit in RS232 uart.Julian Blake Kongslie2022-04-221-0/+23
* Transmit two stop bits to RS232 uart.Julian Blake Kongslie2022-04-221-2/+8
* Working (but very slow) RS232 UARTJulian Blake Kongslie2022-04-171-12/+14
* First pass at RS232 tx/rx modules.Julian Blake Kongslie2022-03-271-0/+131
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-18 22:45:02 -0700