| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Use the DF and IF switches as a selector for which PDP-8 owns the panel. | Julian Blake Kongslie | 2022-03-27 | 1 | -89/+92 |
| * | Add a clock output pin for debugging the PLL. | Julian Blake Kongslie | 2022-03-27 | 1 | -0/+3 |
| * | Reduce internal clock speed to 30MHz. | Julian Blake Kongslie | 2022-03-27 | 1 | -2/+2 |
| * | Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~ | Julian Blake Kongslie | 2022-03-20 | 1 | -41/+113 |
| * | Add memory arbiter and broadcast in between command UART and DRAM. | Julian Blake Kongslie | 2022-03-13 | 1 | -17/+63 |
| * | Change FIFO size for UARTs to 1024 bytes in each direction. | Julian Blake Kongslie | 2022-03-13 | 1 | -2/+2 |
| * | Initial commit. | Julian Blake Kongslie | 2022-02-27 | 1 | -0/+298 |
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index : multipdp8 | |
| Unnamed repository; edit this file 'description' to name the repository. | Julian Blake Kongslie |
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