| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Working L1 cache. | Julian Blake Kongslie | 2022-06-05 | 1 | -0/+1 |
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| * | Consistent RS232 wire names (DCE side names is used everywhere) | Julian Blake Kongslie | 2022-05-15 | 1 | -2/+2 |
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| * | *Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS. | Julian Blake Kongslie | 2022-05-08 | 1 | -1/+48 |
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| * | Working (but very slow) RS232 UART | Julian Blake Kongslie | 2022-04-17 | 1 | -4/+4 |
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| * | Add RX/TX/RTS/CTS pin assignments for future RS232 work. | Julian Blake Kongslie | 2022-03-27 | 1 | -0/+5 |
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| * | Add a clock output pin for debugging the PLL. | Julian Blake Kongslie | 2022-03-27 | 1 | -0/+2 |
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| * | Initial commit. | Julian Blake Kongslie | 2022-02-27 | 2 | -0/+110 |
