hdl/echo_arbiter.sv


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`include "defs.svh"

module echo_arbiter
    (   input   bit         clock
    ,   input   bit         reset

    ,   output  bit         in0_ready
    ,   input   bit         in0_valid
    ,   input   uart_byte_t in0_data

    ,   output  bit         in1_ready
    ,   input   bit         in1_valid
    ,   input   uart_byte_t in1_data

    ,   input   bit         out_ready
    ,   output  bit         out_valid
    ,   output  uart_byte_t out_data
    );

    bit         in0_hold_valid;
    uart_byte_t in0_hold;

    bit         in1_hold_valid;
    uart_byte_t in1_hold;

    always @(posedge clock) begin
        if (reset) begin
            in0_ready = 0;
            in1_ready = 0;
            out_valid = 0;
            out_data = 0;
            in0_hold_valid = 0;
            in0_hold = 0;
            in1_hold_valid = 0;
            in1_hold = 0;
        end else begin
            if (out_ready) out_valid = 0;
            if (in0_ready && in0_valid) begin
                in0_hold_valid = 1;
                in0_hold = in0_data;
            end
            if (in1_ready && in1_valid) begin
                in1_hold_valid = 1;
                in1_hold = in1_data;
            end

            if (!out_valid) begin
                if (in0_hold_valid) begin
                    out_valid = 1;
                    out_data = in0_hold;
                    in0_hold_valid = 0;
                end else if (in1_hold_valid) begin
                    out_valid = 1;
                    out_data = in1_hold;
                    in1_hold_valid = 0;
                end
            end

            in0_ready = !in0_hold_valid;
            in1_ready = !in1_hold_valid;
        end
    end

endmodule