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module fifo
#( WIDTH_BITS = 1
, DEPTH_BITS = 8
)
( input bit clock_in
, input bit clock_out
, input bit reset
, output bit in_ready
, input bit in_valid
, input bit [WIDTH_BITS-1:0] in_data
, input bit out_ready
, output bit out_valid
, output bit [WIDTH_BITS-1:0] out_data
);
localparam DEPTH = 1<<DEPTH_BITS;
typedef bit [WIDTH_BITS-1:0] data_t;
typedef bit [DEPTH_BITS-1:0] addr_t;
typedef bit [DEPTH_BITS:0] grey_t;
(* ramstyle = "no_rw_check, M9K" *) data_t data [DEPTH-1:0];
addr_t oldest, youngest;
bit oldest_wrap, youngest_wrap;
grey_t oldest_grey, oldest_plus_one_wrap_grey, youngest_grey;
always @(posedge clock_in, posedge reset) begin
if (reset) begin
in_ready = 0;
youngest = 0;
youngest_wrap = 0;
youngest_grey = 0;
end else begin
if (in_ready && in_valid) begin
data[youngest] = in_data;
if (++youngest == 0)
++youngest_wrap;
end
youngest_grey = {youngest_wrap, youngest} ^ ({youngest_wrap, youngest} >> 1);
in_ready = oldest_plus_one_wrap_grey != youngest_grey;
end
end
always @(posedge clock_out, posedge reset) begin
if (reset) begin
out_valid = 0;
oldest = 0;
oldest_wrap = 0;
oldest_grey = 0;
oldest_plus_one_wrap_grey = {!oldest_wrap, oldest} ^ ({!oldest_wrap, oldest} >> 1);
end else begin
if (out_ready && out_valid) begin
if (++oldest == 0)
++oldest_wrap;
end
oldest_grey = {oldest_wrap, oldest} ^ ({oldest_wrap, oldest} >> 1);
oldest_plus_one_wrap_grey = {!oldest_wrap, oldest} ^ ({!oldest_wrap, oldest} >> 1);
out_valid = oldest_grey != youngest_grey;
out_data = data[oldest];
end
end
endmodule
|
