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`include "defs.svh"
module mem_broadcast
( input bit clock
, input bit reset
, output bit ram_ready
, input bit ram_valid
, input ram_to_arb_t ram_data
, input bit print_ready
, output bit print_valid
, output ram_to_arb_t print_data
, input bit [`NUM_PDPS-1:0] pdp_ready
, output bit [`NUM_PDPS-1:0] pdp_valid
, output mem_to_core_t [`NUM_PDPS-1:0] pdp_data
);
bit hold_valid;
ram_to_arb_t hold_data;
always @(posedge clock) begin
if (reset) begin
ram_ready = 0;
print_valid = 0;
for (int i = 0; i < `NUM_PDPS; ++i)
pdp_valid[i] = 0;
hold_valid = 0;
end else begin
if (print_ready) print_valid = 0;
for (int i = 0; i < `NUM_PDPS; ++i)
if (pdp_ready[i]) pdp_valid[i] = 0;
if (ram_ready && ram_valid) begin
hold_valid = 1;
hold_data = ram_data;
end
if (hold_valid) begin
if (hold_data.tag == 0) begin
if (!print_valid) begin
print_valid = 1;
print_data = hold_data;
hold_valid = 0;
end
end else begin
if (!pdp_valid[ram_data.tag-1]) begin
pdp_valid[ram_data.tag-1] = 1;
pdp_data[ram_data.tag-1].address = hold_data.address[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)];
pdp_data[ram_data.tag-1].snoop = 0;
pdp_data[ram_data.tag-1].data_valid = 1;
pdp_data[ram_data.tag-1].data = hold_data.data;
hold_valid = 0;
end
end
end
ram_ready = !hold_valid;
end
end
endmodule
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