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|
`include "defs.svh"
module result_printer
#( TAG = 0
) ( input bit clock
, input bit reset
, output bit result_ready
, input bit result_valid
, input ram_read_response_t result_data
, input bit echo_ready
, output bit echo_valid
, output uart_byte_t echo_data
);
ram_read_response_t hold;
ram_byte_count_t byte_count;
ram_word_count_t word_count;
(* syn_encoding = "one-hot" *) enum int unsigned
{ HIGH_NIBBLE
, LOW_NIBBLE
} state;
always @(posedge clock) begin
if (reset) begin
result_ready = 0;
echo_valid = 0;
echo_data = 0;
byte_count = 0;
word_count = 0;
state = state.first;
end else begin
if (echo_ready) echo_valid = 0;
if (result_ready && result_valid) begin
hold = result_data;
if (hold.tag == TAG) begin
byte_count = `RAM_WORD_BYTES;
word_count = `RAM_LINE_WORDS;
state = state.first;
end
end
if (word_count != 0 && !echo_valid) begin
automatic ram_word_t w = hold.data[word_count-1];
automatic ram_byte_t b = w[byte_count-1];
echo_valid = 1;
case (state)
HIGH_NIBBLE: echo_data = b[7:4];
LOW_NIBBLE: echo_data = b[3:0];
endcase
if (echo_data < 10)
echo_data = echo_data + "0";
else
echo_data = echo_data + "A" - 10;
state = state.next;
if (state == state.first) begin
byte_count = byte_count - 1;
if (byte_count == 0) begin
byte_count = `RAM_WORD_BYTES;
word_count = word_count - 1;
end
end
end
result_ready = word_count == 0;
end
end
endmodule
|
