path: root/hdl/top.sv

`include "defs.svh"

module top
    (   input   bit             clock
    ,   input   bit             resetn

    ,   inout   wire    [10:1]  gpioa
    ,   inout   wire    [28:13] gpiob
    ,   inout   wire    [40:31] gpioc

    ,   output  bit             ram_resetn
    ,   output  bit             ram_csn
    ,   output  bit             ram_clkp
    ,   output  bit             ram_clkn
    ,   inout   bit             ram_rwds
    ,   inout   bit     [7:0]   ram_data
    );

    bit internal_clock;
    bit internal_reset;
    pll
        #(  .MULTIPLY_BY(1)
        ,   .DIVIDE_BY(1)
        ) fastpll
        (   .native_clk(clock)
        ,   .reset_n(resetn)
        ,   .target_clk(internal_clock)
        ,   .reset(internal_reset)
        );

    bit         ram_rx_ready;
    bit         ram_rx_valid;
    uart_byte_t ram_rx_data;

    bit         ram_tx_ready;
    bit         ram_tx_valid;
    uart_byte_t ram_tx_data;

    bit         ram_echo_in0_ready;
    bit         ram_echo_in0_valid;
    uart_byte_t ram_echo_in0_data;

    bit         ram_echo_in1_ready;
    bit         ram_echo_in1_valid;
    uart_byte_t ram_echo_in1_data;

    bit             command_ready;
    bit             command_valid;
    ram_command_t   command_data;

    bit                 result_ready;
    bit                 result_valid;
    ram_read_response_t result_data;

    bit         ram_rwds_oe;
    bit         ram_rwds_out;
    assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 1'bZ;

    bit         ram_data_oe;
    bit [7:0]   ram_data_out;
    assign ram_data = ram_data_oe ? ram_data_out : 8'bZ;

    alt_jtag_atlantic
        #(  .INSTANCE_ID(0)
        ,   .LOG2_RXFIFO_DEPTH(6)
        ,   .LOG2_TXFIFO_DEPTH(6)
        ,   .SLD_AUTO_INSTANCE_INDEX("NO")
        ) ram_jtag
        (   .clk(internal_clock)
        ,   .rst_n(!internal_reset)

        ,   .r_dat(ram_tx_data)
        ,   .r_val(ram_tx_valid)
        ,   .r_ena(ram_tx_ready)

        ,   .t_dat(ram_rx_data)
        ,   .t_dav(ram_rx_ready)
        ,   .t_ena(ram_rx_valid)
        );

    echo_arbiter arb
        (   .clock(internal_clock)
        ,   .reset(internal_reset)

        ,   .in0_ready(ram_echo_in0_ready)
        ,   .in0_valid(ram_echo_in0_valid)
        ,   .in0_data(ram_echo_in0_data)

        ,   .in1_ready(ram_echo_in1_ready)
        ,   .in1_valid(ram_echo_in1_valid)
        ,   .in1_data(ram_echo_in1_data)

        ,   .out_ready(ram_tx_ready)
        ,   .out_valid(ram_tx_valid)
        ,   .out_data(ram_tx_data)
        );

    command_parser
        #(  .TAG(0)
        ) parser
        (   .clock(internal_clock)
        ,   .reset(internal_reset)

        ,   .uart_ready(ram_rx_ready)
        ,   .uart_valid(ram_rx_valid)
        ,   .uart_data(ram_rx_data)

        ,   .echo_ready(ram_echo_in0_ready)
        ,   .echo_valid(ram_echo_in0_valid)
        ,   .echo_data(ram_echo_in0_data)

        ,   .command_ready(command_ready)
        ,   .command_valid(command_valid)
        ,   .command_data(command_data)
        );

    ram_controller ram
        (   .clock(internal_clock)
        ,   .reset(internal_reset)

        ,   .command_ready(command_ready)
        ,   .command_valid(command_valid)
        ,   .command_data(command_data)

        ,   .result_ready(result_ready)
        ,   .result_valid(result_valid)
        ,   .result_data(result_data)

        ,   .ram_resetn(ram_resetn)
        ,   .ram_csn(ram_csn)
        ,   .ram_clkp(ram_clkp)
        ,   .ram_clkn(ram_clkn)
        ,   .ram_rwds_oe(ram_rwds_oe)
        ,   .ram_rwds_in(ram_rwds)
        ,   .ram_rwds_out(ram_rwds_out)
        ,   .ram_data_oe(ram_data_oe)
        ,   .ram_data_in(ram_data)
        ,   .ram_data_out(ram_data_out)
        );

    result_printer
        #(  .TAG(0)
        ) print
        (   .clock(internal_clock)
        ,   .reset(internal_reset)

        ,   .result_ready(result_ready)
        ,   .result_valid(result_valid)
        ,   .result_data(result_data)

        ,   .echo_ready(ram_echo_in1_ready)
        ,   .echo_valid(ram_echo_in1_valid)
        ,   .echo_data(ram_echo_in1_data)
        );

    bit slow_clock;
    bit slow_reset;
    pll
        #(  .MULTIPLY_BY(1)
        ,   .DIVIDE_BY(500)
        ) slowpll
        (   .native_clk(clock)
        ,   .reset_n(resetn)
        ,   .target_clk(slow_clock)
        ,   .reset(slow_reset)
        );

    bit [8:1][12:1] led;
    bit [3:1][12:1] switch;

    front_panel panel
        (   .clk(slow_clock)
        ,   .reset(slow_reset)

        ,   .led(led)
        ,   .switch(switch)

        ,   .gpioa(gpioa)
        ,   .gpiob(gpiob)
        ,   .gpioc(gpioc)
        );

    bit [2:0] switch_df;
    bit [2:0] switch_if;
    bit [11:0] switch_sr;
    bit switch_start;
    bit switch_load_add;
    bit switch_dep;
    bit switch_exam;
    bit switch_cont;
    bit switch_stop;
    bit switch_sing_step;
    bit switch_sing_inst;

    // Note that we are reversing the order here on a number of aggregates because
    // the panel model gives us LEDs and switches in schematic-order, which is the
    // opposite of the bit order
    assign switch_df = {switch[2][1], switch[2][2], switch[2][3]};
    assign switch_if = {switch[2][4], switch[2][5], switch[2][6]};
    assign switch_sr = {switch[1][1], switch[1][2], switch[1][3], switch[1][4], switch[1][5], switch[1][6], switch[1][7], switch[1][8], switch[1][9], switch[1][10], switch[1][11], switch[1][12]};
    assign switch_start = switch[3][1];
    assign switch_load_add = switch[3][2];
    assign switch_dep = switch[3][3];
    assign switch_exam = switch[3][4];
    assign switch_cont = switch[3][5];
    assign switch_stop = switch[3][6];
    `ifdef HISTORIC_SWITCH_BEHAVIOUR
    assign switch_sing_step = !switch[3][7];
    assign switch_sing_inst = !switch[3][8];
    `else
    assign switch_sing_step = switch[3][7];
    assign switch_sing_inst = switch[3][8];
    `endif

    bit [11:0] led_pc;
    bit [11:0] led_memaddr;
    bit [11:0] led_memdata;
    bit [11:0] led_acc;
    bit [11:0] led_mq;
    bit led_and;
    bit led_tad;
    bit led_isz;
    bit led_dca;
    bit led_jms;
    bit led_jmp;
    bit led_iot;
    bit led_opr;
    bit led_fetch;
    bit led_execute;
    bit led_defer;
    bit led_word_count;
    bit led_current_address;
    bit led_break;
    bit led_ion;
    bit led_pause;
    bit led_run;
    bit [4:0] led_step_counter;
    bit [2:0] led_df;
    bit [2:0] led_if;
    bit led_link;

    // Note that we are reversing the order here on a number of aggregates because
    // the panel model gives us LEDs and switches in schematic-order, which is the
    // opposite of the bit order
    assign led[1] = {led_pc[0], led_pc[1], led_pc[2], led_pc[3], led_pc[4], led_pc[5], led_pc[6], led_pc[7], led_pc[8], led_pc[9], led_pc[10], led_pc[11]};
    assign led[2] = {led_memaddr[0], led_memaddr[1], led_memaddr[2], led_memaddr[3], led_memaddr[4], led_memaddr[5], led_memaddr[6], led_memaddr[7], led_memaddr[8], led_memaddr[9], led_memaddr[10], led_memaddr[11]};
    assign led[3] = {led_memdata[0], led_memdata[1], led_memdata[2], led_memdata[3], led_memdata[4], led_memdata[5], led_memdata[6], led_memdata[7], led_memdata[8], led_memdata[9], led_memdata[10], led_memdata[11]};
    assign led[4] = {led_acc[0], led_acc[1], led_acc[2], led_acc[3], led_acc[4], led_acc[5], led_acc[6], led_acc[7], led_acc[8], led_acc[9], led_acc[10], led_acc[11]};
    assign led[5] = {led_mq[0], led_mq[1], led_mq[2], led_mq[3], led_mq[4], led_mq[5], led_mq[6], led_mq[7], led_mq[8], led_mq[9], led_mq[10], led_mq[11]};
    assign led[6] = {led_word_count, led_defer, led_execute, led_fetch, led_opr, led_iot, led_jmp, led_jms, led_dca, led_isz, led_tad, led_and};
    assign led[7] = {2'b0, led_step_counter[4], led_step_counter[3], led_step_counter[2], led_step_counter[1], led_step_counter[0], led_run, led_pause, led_ion, led_break, led_current_address};
    assign led[8] = {5'b0, led_link, led_if[0], led_if[1], led_if[2], led_df[0], led_df[1], led_df[2]};

    core cpu
        (   .clk(internal_clock)
        ,   .reset(internal_reset)

        ,   .switch_df(switch_df)
        ,   .switch_if(switch_if)
        ,   .switch_sr(switch_sr)
        ,   .switch_start(switch_start)
        ,   .switch_load_add(switch_load_add)
        ,   .switch_dep(switch_dep)
        ,   .switch_exam(switch_exam)
        ,   .switch_cont(switch_cont)
        ,   .switch_stop(switch_stop)
        ,   .switch_sing_step(switch_sing_step)
        ,   .switch_sing_inst(switch_sing_inst)

        ,   .led_pc(led_pc)
        ,   .led_memaddr(led_memaddr)
        ,   .led_memdata(led_memdata)
        ,   .led_acc(led_acc)
        ,   .led_mq(led_mq)
        ,   .led_and(led_and)
        ,   .led_tad(led_tad)
        ,   .led_isz(led_isz)
        ,   .led_dca(led_dca)
        ,   .led_jms(led_jms)
        ,   .led_jmp(led_jmp)
        ,   .led_iot(led_iot)
        ,   .led_opr(led_opr)
        ,   .led_fetch(led_fetch)
        ,   .led_execute(led_execute)
        ,   .led_defer(led_defer)
        ,   .led_word_count(led_word_count)
        ,   .led_current_address(led_current_address)
        ,   .led_break(led_break)
        ,   .led_ion(led_ion)
        ,   .led_pause(led_pause)
        ,   .led_run(led_run)
        ,   .led_step_counter(led_step_counter)
        ,   .led_df(led_df)
        ,   .led_if(led_if)
        ,   .led_link(led_link)
        );

endmodule