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authorJulian Blake Kongslie2021-04-15 16:39:30 -0700
committerJulian Blake Kongslie2021-04-15 16:39:30 -0700
commit4203007c5ac99c6f46b2aea378d043511b2d798d (patch)
treea100bc17e2a1dd5e9b87f0002e4a91c400559b4c /altera/clocks.sdc
parentMore makefile corrections/simplifications for quartus on Linux. (diff)
downloadnoncpu-4203007c5ac99c6f46b2aea378d043511b2d798d.tar.xz
Fix timing declarations for PLL in Quartus assignments.
Diffstat (limited to 'altera/clocks.sdc')
-rw-r--r--altera/clocks.sdc1
1 files changed, 1 insertions, 0 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index 15d4482..1febf5c 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,4 @@
1# This is the clock for timing analysis, not timing-driven synthesis. 1# This is the clock for timing analysis, not timing-driven synthesis.
2# See init.tcl for the other clock. 2# See init.tcl for the other clock.
3create_clock -period "50 MHz" native_clk
3create_clock -period "45 MHz" clk 4create_clock -period "45 MHz" clk