Change our simulator timing model to use continuous assignment guards.

Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.

1 files changed, 25 insertions, 18 deletions

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index ad4665e..2b5f334 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -9,15 +9,22 @@ module jtag_uart
     (   input   bit clk
     ,   input   bit reset
 
-    ,   input   bit         rx_ready    `define rx_ready `past(rx_ready)
+    ,   input   bit         rx_ready
     ,   output  bit         rx_valid
     ,   output  bit [7:0]   rx_data
 
     ,   output  bit         tx_ready
-    ,   input   bit         tx_valid    `define tx_valid `past(tx_valid)
-    ,   input   bit [7:0]   tx_data     `define tx_data `past(tx_data)
+    ,   input   bit         tx_valid
+    ,   input   bit [7:0]   tx_data
     );
 
+`input(rx_ready)
+`output(rx_valid)
+`output(rx_data)
+`output(tx_ready)
+`input(tx_valid)
+`input(tx_data)
+
 `ifdef SYNTHESIS
 
 alt_jtag_atlantic
@@ -28,12 +35,12 @@ alt_jtag_atlantic
     ) real_jtag
     (   .clk(clk)
     ,   .rst_n(!reset)
-    ,   .r_dat(tx_data)
-    ,   .r_val(tx_valid)
-    ,   .r_ena(tx_ready)
-    ,   .t_dat(rx_data)
-    ,   .t_dav(rx_ready)
-    ,   .t_ena(rx_valid)
+    ,   .r_dat(tx_data_)
+    ,   .r_val(tx_valid_)
+    ,   .r_ena(tx_ready_)
+    ,   .t_dat(rx_data_)
+    ,   .t_dav(rx_ready_)
+    ,   .t_ena(rx_valid_)
     );
 
 `else
@@ -48,34 +55,34 @@ bit [7:0] tx_b_data;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        rx_valid = 0;
-        tx_ready = 0;
+        rx_valid_ = 0;
+        tx_ready_ = 0;
         sim_rx_addr = 0;
         tx_b_valid = 0;
     end else begin
         automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
 
         // RX logic
-        if (`rx_ready) rx_valid = 0;
-        if (!rx_valid && (sim_rx_data != 0)) begin
+        if (rx_ready_) rx_valid_ = 0;
+        if (!rx_valid_ && (sim_rx_data != 0)) begin
 `ifdef JTAG_UART_LOCAL_ECHO
             $write("%s", sim_rx_data);
 `endif
-            rx_valid = 1;
-            rx_data = sim_rx_data;
+            rx_valid_ = 1;
+            rx_data_ = sim_rx_data;
             ++sim_rx_addr;
         end
 
         // TX logic
-        if (tx_ready && `tx_valid) begin
+        if (tx_ready_ && tx_valid_) begin
             tx_b_valid = 1;
-            tx_b_data = `tx_data;
+            tx_b_data = tx_data_;
         end
         if (tx_b_valid) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
-        tx_ready = !tx_b_valid;
+        tx_ready_ = !tx_b_valid;
     end
 end