diff options
| author | Julian Blake Kongslie | 2021-04-15 16:39:58 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2021-04-15 16:39:58 -0700 |
| commit | abd9703a1b96225db0d7317bf8833467150bae26 (patch) | |
| tree | 1cafad36a4e4773b32fa38e6ca16fa0ca37dcbd1 /hdl/top.sv | |
| parent | Fix timing declarations for PLL in Quartus assignments. (diff) | |
| download | noncpu-abd9703a1b96225db0d7317bf8833467150bae26.tar.xz | |
Change synthesis of PLL wrapper to avoid latch logic.pre-dp-8
Diffstat (limited to '')
| -rw-r--r-- | hdl/top.sv | 4 |
1 files changed, 2 insertions, 2 deletions
| @@ -12,8 +12,8 @@ bit clk; | |||
| 12 | bit reset; | 12 | bit reset; |
| 13 | 13 | ||
| 14 | clock | 14 | clock |
| 15 | #( .DIVIDE_BY(10) | 15 | #( .MULTIPLY_BY(9) |
| 16 | , .MULTIPLY_BY(9) | 16 | , .DIVIDE_BY(10) |
| 17 | ) pll | 17 | ) pll |
| 18 | ( .native_clk(native_clk) | 18 | ( .native_clk(native_clk) |
| 19 | , .reset_n(reset_n) | 19 | , .reset_n(reset_n) |