Use internal PLL for clock and reset generation.

1 files changed, 14 insertions, 6 deletions

diff --git a/hdl/top.sv b/hdl/top.sv
index 8d83f35..46620cb 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -4,14 +4,22 @@ module top
     #(  ADDR_BITS   = 14
     ,   DATA_BITS   = 12
     )
-    (   input   bit clk     // verilator public
-    ,   input   bit reset_n // verilator public
+    (   input   bit native_clk  // verilator public
+    ,   input   bit reset_n     // verilator public
     );
 
-bit reset = 0;
-bit have_reset = 0;
-always_ff @(posedge clk) if (reset) have_reset <= 1;
-assign reset = !reset_n || !have_reset;
+bit clk;
+bit reset;
+
+clock
+    #(  .DIVIDE_BY(10)
+    ,   .MULTIPLY_BY(9)
+    ) pll
+    (   .native_clk(native_clk)
+    ,   .reset_n(reset_n)
+    ,   .target_clk(clk)
+    ,   .reset(reset)
+    );
 
 bit mem_ready;
 bit mem_valid;