Change our simulator timing model to use continuous assignment guards.

Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.

1 files changed, 2 insertions, 5 deletions

diff --git a/hdl/util.svh b/hdl/util.svh
index db5e4e6..fa6ddc5 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,5 +1,2 @@
-`ifdef SYNTHESIS
-`define past(x) x
-`else
-`define past(x) $sampled(x)
-`endif
+`define input(x) type(x) x``_; assign x``_ = x;
+`define output(x) type(x) x``_; assign x = x``_;