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authorJulian Blake Kongslie2021-11-21 15:56:53 -0800
committerJulian Blake Kongslie2021-11-21 15:56:53 -0800
commitafcb3330709e357970a908e3396fe377f28a7222 (patch)
tree21ba50429351963b1ddfd6bf7d7556646a69b3e6 /hdl
parentImplement switches Start and LoadAdd. (diff)
downloadnoncpu-afcb3330709e357970a908e3396fe377f28a7222.tar.xz
Interrupt-driven keyboard input.
Diffstat (limited to 'hdl')
-rw-r--r--hdl/core.sv87
-rw-r--r--hdl/top.sv2
2 files changed, 77 insertions, 12 deletions
diff --git a/hdl/core.sv b/hdl/core.sv
index 14660f5..b607e4b 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -50,12 +50,18 @@ module core
50 ); 50 );
51 51
52bit run; 52bit run;
53bit int_enable;
54bit int_delay;
55bit int_request;
56
53bit switch_start_observed; 57bit switch_start_observed;
54bit switch_load_add_observed; 58bit switch_load_add_observed;
55bit switch_dep_observed; 59bit switch_dep_observed;
56bit switch_exam_observed; 60bit switch_exam_observed;
57bit switch_cont_observed; 61bit switch_cont_observed;
62
58assign led_run = run; 63assign led_run = run;
64assign led_ion = int_enable;
59 65
60bit mem_ready; 66bit mem_ready;
61bit mem_valid; 67bit mem_valid;
@@ -134,14 +140,19 @@ assign led_jmp = opcode == 5;
134assign led_iot = opcode == 6; 140assign led_iot = opcode == 6;
135assign led_opr = opcode == 7; 141assign led_opr = opcode == 7;
136 142
137bit kbd_valid; 143bit tti_int_enable;
138bit [DATA_BITS-1:0] kbd_data; 144bit tti_valid;
145bit [DATA_BITS-1:0] tti_data;
139 146
140bit i; 147bit i;
141bit z; 148bit z;
142bit [6:0] wip; 149bit [6:0] wip;
143bit [ADDR_BITS-1:0] address; 150bit [ADDR_BITS-1:0] address;
144 151
152assign int_request =
153 (tti_int_enable && tti_valid)
154 ;
155
145enum 156enum
146 { FETCH 157 { FETCH
147 , DECODE 158 , DECODE
@@ -162,6 +173,8 @@ assign led_pause = state == MEMWAIT || state == HALT;
162always_ff @(posedge clk) begin 173always_ff @(posedge clk) begin
163 if (reset) begin 174 if (reset) begin
164 run = 0; 175 run = 0;
176 int_enable = 0;
177 int_delay = 0;
165 switch_start_observed = 0; 178 switch_start_observed = 0;
166 switch_load_add_observed = 0; 179 switch_load_add_observed = 0;
167 switch_dep_observed = 0; 180 switch_dep_observed = 0;
@@ -175,12 +188,15 @@ always_ff @(posedge clk) begin
175 led_pc = pc; 188 led_pc = pc;
176 acc = 0; 189 acc = 0;
177 link = 1; 190 link = 1;
178 kbd_valid = 0; 191 tti_int_enable = 0;
192 tti_valid = 0;
179 state = state.first; 193 state = state.first;
180 end else begin 194 end else begin
181 if (switch_start && !switch_start_observed) begin 195 if (switch_start && !switch_start_observed) begin
182 switch_start_observed = 1; 196 switch_start_observed = 1;
183 run = 1; 197 run = 1;
198 int_enable = 0;
199 int_delay = 0;
184 mem_valid = 0; 200 mem_valid = 0;
185 acc = 0; 201 acc = 0;
186 link = 1; 202 link = 1;
@@ -226,8 +242,8 @@ always_ff @(posedge clk) begin
226 242
227 if (`lag(tx_ready)) tx_valid = 0; 243 if (`lag(tx_ready)) tx_valid = 0;
228 if (rx_ready && `lag(rx_valid)) begin 244 if (rx_ready && `lag(rx_valid)) begin
229 kbd_valid = 1; 245 tti_valid = 1;
230 kbd_data = {4'b0, 1'b1, `lag(rx_data[6:0])}; 246 tti_data = {4'b0, 1'b1, `lag(rx_data[6:0])};
231 end 247 end
232 248
233 if (run) begin 249 if (run) begin
@@ -245,12 +261,25 @@ always_ff @(posedge clk) begin
245 end 261 end
246 262
247 DECODE: begin 263 DECODE: begin
264 automatic bit go;
265 go = 0;
248 mem_valid = 0; 266 mem_valid = 0;
249 mem_write = 0; 267 mem_write = 0;
250 if (`lag(mem_read_valid)) begin 268 if (int_enable && int_request) begin
269 int_enable = 0;
270 int_delay = 0;
271 --pc;
272 opcode = 'b100;
273 operand = 'b000000;
274 go = 1;
275 end else if (`lag(mem_read_valid)) begin
251 state = FETCH; 276 state = FETCH;
252 led_memdata = `lag(mem_read_data); 277 led_memdata = `lag(mem_read_data);
253 {opcode, operand} = `lag(mem_read_data); 278 {opcode, operand} = `lag(mem_read_data);
279 go = 1;
280 end
281 if (go) begin
282 int_enable = int_delay;
254 // $display("%o: decode %o %o", pc-1, opcode, operand); 283 // $display("%o: decode %o %o", pc-1, opcode, operand);
255 // verilator lint_off WIDTH 284 // verilator lint_off WIDTH
256 // $display("%o %b %o 0000", 14'(pc-1), link, acc); 285 // $display("%o %b %o 0000", 14'(pc-1), link, acc);
@@ -332,16 +361,51 @@ always_ff @(posedge clk) begin
332 case (operand[8:3]) 361 case (operand[8:3])
333 'o00: begin 362 'o00: begin
334 case (operand[2:0]) 363 case (operand[2:0])
335 'o0, 'o1: ; 364 'o0: begin
365 if (int_enable)
366 ++pc;
367 int_enable = 0;
368 int_delay = 0;
369 end
370 'o1: int_delay = 1;
371 'o2: begin
372 int_enable = 0;
373 int_delay = 0;
374 end
375 'o3: begin
376 if (int_request)
377 ++pc;
378 end
379 'o4: acc = {link, 1'b0/*gt*/, int_request, 1'b0/*ii*/, int_enable, 1'b0/*u*/, 3'b0/*if*/, 3'b0/*df*/};
380 'o5: begin
381 link = acc[11];
382 if (acc[7]) begin
383 int_delay = 1;
384 end else begin
385 int_enable = 0;
386 int_delay = 0;
387 end
388 end
389 'o7: begin
390 int_enable = 0;
391 int_delay = 0;
392 acc = 0;
393 link = 1;
394 tx_valid = 0;
395 tti_valid = 0;
396 end
336 default: $display("%o: unsupported 600%o op", pc-1, operand[2:0]); 397 default: $display("%o: unsupported 600%o op", pc-1, operand[2:0]);
337 endcase 398 endcase
338 end 399 end
339 'o03: begin 400 'o03: begin
340 case (operand[2:0]) 401 case (operand[2:0])
341 'o1: if (kbd_valid) pc++; 402 'o1: if (tti_valid) pc++;
403 'o5: begin
404 tti_int_enable = acc[0];
405 end
342 'o6: begin 406 'o6: begin
343 acc = kbd_data; 407 acc = tti_data;
344 kbd_valid = 0; 408 tti_valid = 0;
345 end 409 end
346 default: begin 410 default: begin
347 $display("%o: unsupported keyboard op %o", pc-1, operand[2:0]); 411 $display("%o: unsupported keyboard op %o", pc-1, operand[2:0]);
@@ -479,6 +543,7 @@ always_ff @(posedge clk) begin
479 MEMWAIT: state = `lag(mem_ready) ? FETCH : MEMWAIT; 543 MEMWAIT: state = `lag(mem_ready) ? FETCH : MEMWAIT;
480 544
481 HALT: begin 545 HALT: begin
546 run = 0;
482 $display("\nhalt state reached"); 547 $display("\nhalt state reached");
483 $finish; 548 $finish;
484 end 549 end
@@ -490,7 +555,7 @@ always_ff @(posedge clk) begin
490 if (state == FETCH && switch_sing_inst) 555 if (state == FETCH && switch_sing_inst)
491 run = 0; 556 run = 0;
492 557
493 rx_ready = !kbd_valid; 558 rx_ready = !tti_valid;
494 end 559 end
495 end 560 end
496end 561end
diff --git a/hdl/top.sv b/hdl/top.sv
index 8ed2bc6..67e3437 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -112,7 +112,7 @@ assign led[3] = {led_memdata[0], led_memdata[1], led_memdata[2], led_memdata[3],
112assign led[4] = {led_acc[0], led_acc[1], led_acc[2], led_acc[3], led_acc[4], led_acc[5], led_acc[6], led_acc[7], led_acc[8], led_acc[9], led_acc[10], led_acc[11]}; 112assign led[4] = {led_acc[0], led_acc[1], led_acc[2], led_acc[3], led_acc[4], led_acc[5], led_acc[6], led_acc[7], led_acc[8], led_acc[9], led_acc[10], led_acc[11]};
113assign led[5] = {led_mq[0], led_mq[1], led_mq[2], led_mq[3], led_mq[4], led_mq[5], led_mq[6], led_mq[7], led_mq[8], led_mq[9], led_mq[10], led_mq[11]}; 113assign led[5] = {led_mq[0], led_mq[1], led_mq[2], led_mq[3], led_mq[4], led_mq[5], led_mq[6], led_mq[7], led_mq[8], led_mq[9], led_mq[10], led_mq[11]};
114assign led[6] = {led_word_count, led_defer, led_execute, led_fetch, led_opr, led_iot, led_jmp, led_jms, led_dca, led_isz, led_tad, led_and}; 114assign led[6] = {led_word_count, led_defer, led_execute, led_fetch, led_opr, led_iot, led_jmp, led_jms, led_dca, led_isz, led_tad, led_and};
115assign led[7] = {2'b0, led_step_counter, led_run, led_pause, led_ion, led_break, led_current_address}; 115assign led[7] = {2'b0, led_step_counter[4], led_step_counter[3], led_step_counter[2], led_step_counter[1], led_step_counter[0], led_run, led_pause, led_ion, led_break, led_current_address};
116assign led[8] = {5'b0, led_link, led_if[0], led_if[1], led_if[2], led_df[0], led_df[1], led_df[2]}; 116assign led[8] = {5'b0, led_link, led_if[0], led_if[1], led_if[2], led_df[0], led_df[1], led_df[2]};
117 117
118core cpu 118core cpu