3 files changed, 286 insertions, 3 deletions
diff --git a/hdl/panel.sv b/hdl/panel.sv
new file mode 100644
index 0000000..fc1f718
--- /dev/null
+++ b/hdl/panel.sv
@@ -0,0 +1,184 @@
+`include "util.svh"
+module panel
+    (   input   bit clk
+    ,   input   bit reset
+    ,   input   bit [8:1][12:1] led
+    ,   output  bit [3:1][12:1] switch
+    ,   inout   wire [10:1]  gpioa
+    ,   inout   wire [28:13] gpiob
+    ,   inout   wire [40:31] gpioc
+    );
+enum
+    {   LED_ROW1
+    ,   LED_ROW2
+    ,   LED_ROW3
+    ,   LED_ROW4
+    ,   LED_ROW5
+    ,   LED_ROW6
+    ,   LED_ROW7
+    ,   LED_ROW8
+    ,   SWITCH_PREP
+    ,   SWITCH_ROW1
+    ,   SWITCH_ROW2
+    ,   SWITCH_ROW3
+    } state;
+`define LEDROW1 gpioc[38]
+`define LEDROW2 gpioc[40]
+`define LEDROW3 gpiob[15]
+`define LEDROW4 gpiob[16]
+`define LEDROW5 gpiob[18]
+`define LEDROW6 gpiob[22]
+`define LEDROW7 gpioc[37]
+`define LEDROW8 gpiob[13]
+`define SWROW1  gpioc[36]
+`define SWROW2  gpioa[1]
+`define SWROW3  gpioa[2]
+`define COL1    gpioa[8]
+`define COL2    gpioa[10]
+`define COL3    gpioa[7]
+`define COL4    gpiob[27]
+`define COL5    gpioc[31]
+`define COL6    gpiob[26]
+`define COL7    gpiob[24]
+`define COL8    gpiob[21]
+`define COL9    gpiob[19]
+`define COL10   gpiob[23]
+`define COL11   gpioc[32]
+`define COL12   gpioc[33]
+`define DO_LEDS
+`define DO_SWITCHES
+always_ff @(posedge clk) begin
+    // LED rows (active high)
+    `LEDROW1    = 1'b0;
+    `LEDROW2    = 1'b0;
+    `LEDROW3    = 1'b0;
+    `LEDROW4    = 1'b0;
+    `LEDROW5    = 1'b0;
+    `LEDROW6    = 1'b0;
+    `LEDROW7    = 1'b0;
+    `LEDROW8    = 1'b0;
+    // Switch rows (active low)
+    `SWROW1     = 1'b1;
+    `SWROW2     = 1'b1;
+    `SWROW3     = 1'b1;
+    if (reset) begin
+        switch = 0;
+        state = state.first;
+    end else begin
+        case (state)
+`ifdef DO_LEDS
+`define LED_ROW(n) \
+            LED_ROW``n: begin \
+                `LEDROW``n  = 1'b1; \
+                `COL1       = ~led[n][1]; \
+                `COL2       = ~led[n][2]; \
+                `COL3       = ~led[n][3]; \
+                `COL4       = ~led[n][4]; \
+                `COL5       = ~led[n][5]; \
+                `COL6       = ~led[n][6]; \
+                `COL7       = ~led[n][7]; \
+                `COL8       = ~led[n][8]; \
+                `COL9       = ~led[n][9]; \
+                `COL10      = ~led[n][10]; \
+                `COL11      = ~led[n][11]; \
+                `COL12      = ~led[n][12]; \
+            end
+            `LED_ROW(1)
+            `LED_ROW(2)
+            `LED_ROW(3)
+            `LED_ROW(4)
+            `LED_ROW(5)
+            `LED_ROW(6)
+            `LED_ROW(7)
+            `LED_ROW(8)
+`endif
+`ifdef DO_SWITCHES
+            SWITCH_PREP: begin
+                `SWROW1 = 1'b0;
+                `COL1   = 1'bZ;
+                `COL2   = 1'bZ;
+                `COL3   = 1'bZ;
+                `COL4   = 1'bZ;
+                `COL5   = 1'bZ;
+                `COL6   = 1'bZ;
+                `COL7   = 1'bZ;
+                `COL8   = 1'bZ;
+                `COL9   = 1'bZ;
+                `COL10  = 1'bZ;
+                `COL11  = 1'bZ;
+                `COL12  = 1'bZ;
+            end
+            SWITCH_ROW1: begin
+                `SWROW2 = 1'b0;
+                switch[1][1]    = ~`COL1;
+                switch[1][2]    = ~`COL2;
+                switch[1][3]    = ~`COL3;
+                switch[1][4]    = ~`COL4;
+                switch[1][5]    = ~`COL5;
+                switch[1][6]    = ~`COL6;
+                switch[1][7]    = ~`COL7;
+                switch[1][8]    = ~`COL8;
+                switch[1][9]    = ~`COL9;
+                switch[1][10]   = ~`COL10;
+                switch[1][11]   = ~`COL11;
+                switch[1][12]   = ~`COL12;
+            end
+            SWITCH_ROW2: begin
+                `SWROW3 = 1'b0;
+                switch[2][1]    = ~`COL1;
+                switch[2][2]    = ~`COL2;
+                switch[2][3]    = ~`COL3;
+                switch[2][4]    = ~`COL4;
+                switch[2][5]    = ~`COL5;
+                switch[2][6]    = ~`COL6;
+                switch[2][7]    = ~`COL7;
+                switch[2][8]    = ~`COL8;
+                switch[2][9]    = ~`COL9;
+                switch[2][10]   = ~`COL10;
+                switch[2][11]   = ~`COL11;
+                switch[2][12]   = ~`COL12;
+            end
+            SWITCH_ROW3: begin
+                switch[3][1]    = ~`COL1;
+                switch[3][2]    = ~`COL2;
+                switch[3][3]    = ~`COL3;
+                switch[3][4]    = ~`COL4;
+                switch[3][5]    = ~`COL5;
+                switch[3][6]    = ~`COL6;
+                switch[3][7]    = ~`COL7;
+                switch[3][8]    = ~`COL8;
+                switch[3][9]    = ~`COL9;
+                switch[3][10]   = ~`COL10;
+                switch[3][11]   = ~`COL11;
+                switch[3][12]   = ~`COL12;
+            end
+`endif
+        endcase
+        if (state == state.last)
+            state = state.first;
+        else
+            state = state.next;
+    end
+end
+endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
index 1d77216..abd6f30 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -3,6 +3,10 @@
 module top
    (   input   bit native_clk  // verilator public
    ,   input   bit reset_n     // verilator public
+    ,   inout   wire [10:1]  gpioa
+    ,   inout   wire [28:13] gpiob
+    ,   inout   wire [40:31] gpioc
    );
 bit clk;
@@ -18,9 +22,61 @@ clock
    ,   .reset(reset)
    );
+bit slowclk;
+bit slowreset;
+clock
+    #(  .MULTIPLY_BY(1)
+    ,   .DIVIDE_BY(5000)
+    ) slowpll
+    (   .native_clk(native_clk)
+    ,   .reset_n(reset_n)
+    ,   .target_clk(slowclk)
+    ,   .reset(slowreset)
+    );
+bit [8:1][12:1] led;
+bit [3:1][12:1] switch;
+panel fp
+    (   .clk(slowclk)
+    ,   .reset(slowreset)
+    ,   .led(led)
+    ,   .switch(switch)
+    ,   .gpioa(gpioa)
+    ,   .gpiob(gpiob)
+    ,   .gpioc(gpioc)
+    );
+assign led[1] = switch[1];
+assign led[2] = switch[2];
+assign led[3] = switch[3];
+assign led[4] = 0;
+assign led[5] = 0;
+assign led[6] = 0;
+assign led[7] = 0;
+assign led[8] = 0;
+/*
+wire [7:0] debugchar;
+assign debugchar = "0" + {switch[1][1], switch[1][2], switch[3][1]};
+jtag_uart debug
+    (   .clk(slowclk)
+    ,   .reset(slowreset)
+    ,   .rx_ready(0)
+    ,   .tx_valid(1)
+    ,   .tx_data(debugchar)
+    );
+*/
+/*
 core cpu
    (   .clk(clk)
    ,   .reset(reset)
    );
+*/
 endmodule
diff --git a/tcl/init.tcl b/tcl/init.tcl
index 3466f17..9f296f3 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -6,13 +6,56 @@ set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
-proc pin {loc net} {
+proc pin {net loc} {
    set_location_assignment -to $net "PIN_$loc"
    set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
 }
-pin E1  native_clk
+proc iopin {net loc} {
-pin J15 reset_n
+    pin $net $loc
+    set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to $net
+}
+pin native_clk  E1
+iopin reset_n   J15
+iopin gpioa[1]    L13
+iopin gpioa[2]    L16
+iopin gpioa[3]    L15
+iopin gpioa[4]    K16
+iopin gpioa[5]    P16
+iopin gpioa[6]    R16
+iopin gpioa[7]    N16
+iopin gpioa[8]    N15
+iopin gpioa[9]    N14
+iopin gpioa[10]   P15
+iopin gpiob[13]   N8
+iopin gpiob[14]   P8
+iopin gpiob[15]   M8
+iopin gpiob[16]   L8
+iopin gpiob[17]   R7
+iopin gpiob[18]   T7
+iopin gpiob[19]   L7
+iopin gpiob[20]   M7
+iopin gpiob[21]   R6
+iopin gpiob[22]   T6
+iopin gpiob[23]   T2
+iopin gpiob[24]   M6
+iopin gpiob[25]   R5
+iopin gpiob[26]   T5
+iopin gpiob[27]   N5
+iopin gpiob[28]   N6
+iopin gpioc[31]   R4
+iopin gpioc[32]   T4
+iopin gpioc[33]   N3
+iopin gpioc[34]   P3
+iopin gpioc[35]   R3
+iopin gpioc[36]   T3
+iopin gpioc[37]   P6
+iopin gpioc[38]   P2
+iopin gpioc[39]   P1
+iopin gpioc[40]   R1
 # This is the clock for timing-driven synthesis, not timing analysis.
 # See clocks.sdf for the other clock.

diff --git a/hdl/panel.sv b/hdl/panel.sv new file mode 100644 index 0000000..fc1f718 --- /dev/null +++ b/hdl/panel.sv
@@ -0,0 +1,184 @@
		1	`include "util.svh"
		2
		3	module panel
		4	( input bit clk
		5	, input bit reset
		6
		7	, input bit [8:1][12:1] led
		8	, output bit [3:1][12:1] switch
		9
		10	, inout wire [10:1] gpioa
		11	, inout wire [28:13] gpiob
		12	, inout wire [40:31] gpioc
		13	);
		14
		15	enum
		16	{ LED_ROW1
		17	, LED_ROW2
		18	, LED_ROW3
		19	, LED_ROW4
		20	, LED_ROW5
		21	, LED_ROW6
		22	, LED_ROW7
		23	, LED_ROW8
		24	, SWITCH_PREP
		25	, SWITCH_ROW1
		26	, SWITCH_ROW2
		27	, SWITCH_ROW3
		28	} state;
		29
		30	`define LEDROW1 gpioc[38]
		31	`define LEDROW2 gpioc[40]
		32	`define LEDROW3 gpiob[15]
		33	`define LEDROW4 gpiob[16]
		34	`define LEDROW5 gpiob[18]
		35	`define LEDROW6 gpiob[22]
		36	`define LEDROW7 gpioc[37]
		37	`define LEDROW8 gpiob[13]
		38
		39	`define SWROW1 gpioc[36]
		40	`define SWROW2 gpioa[1]
		41	`define SWROW3 gpioa[2]
		42
		43	`define COL1 gpioa[8]
		44	`define COL2 gpioa[10]
		45	`define COL3 gpioa[7]
		46	`define COL4 gpiob[27]
		47	`define COL5 gpioc[31]
		48	`define COL6 gpiob[26]
		49	`define COL7 gpiob[24]
		50	`define COL8 gpiob[21]
		51	`define COL9 gpiob[19]
		52	`define COL10 gpiob[23]
		53	`define COL11 gpioc[32]
		54	`define COL12 gpioc[33]
		55
		56	`define DO_LEDS
		57	`define DO_SWITCHES
		58
		59	always_ff @(posedge clk) begin
		60	// LED rows (active high)
		61	`LEDROW1 = 1'b0;
		62	`LEDROW2 = 1'b0;
		63	`LEDROW3 = 1'b0;
		64	`LEDROW4 = 1'b0;
		65	`LEDROW5 = 1'b0;
		66	`LEDROW6 = 1'b0;
		67	`LEDROW7 = 1'b0;
		68	`LEDROW8 = 1'b0;
		69
		70	// Switch rows (active low)
		71	`SWROW1 = 1'b1;
		72	`SWROW2 = 1'b1;
		73	`SWROW3 = 1'b1;
		74
		75	if (reset) begin
		76	switch = 0;
		77	state = state.first;
		78	end else begin
		79	case (state)
		80	`ifdef DO_LEDS
		81	`define LED_ROW(n) \
		82	LED_ROW``n: begin \
		83	`LEDROW``n = 1'b1; \
		84	`COL1 = ~led[n][1]; \
		85	`COL2 = ~led[n][2]; \
		86	`COL3 = ~led[n][3]; \
		87	`COL4 = ~led[n][4]; \
		88	`COL5 = ~led[n][5]; \
		89	`COL6 = ~led[n][6]; \
		90	`COL7 = ~led[n][7]; \
		91	`COL8 = ~led[n][8]; \
		92	`COL9 = ~led[n][9]; \
		93	`COL10 = ~led[n][10]; \
		94	`COL11 = ~led[n][11]; \
		95	`COL12 = ~led[n][12]; \
		96	end
		97
		98	`LED_ROW(1)
		99	`LED_ROW(2)
		100	`LED_ROW(3)
		101	`LED_ROW(4)
		102	`LED_ROW(5)
		103	`LED_ROW(6)
		104	`LED_ROW(7)
		105	`LED_ROW(8)
		106	`endif
		107
		108	`ifdef DO_SWITCHES
		109	SWITCH_PREP: begin
		110	`SWROW1 = 1'b0;
		111
		112	`COL1 = 1'bZ;
		113	`COL2 = 1'bZ;
		114	`COL3 = 1'bZ;
		115	`COL4 = 1'bZ;
		116	`COL5 = 1'bZ;
		117	`COL6 = 1'bZ;
		118	`COL7 = 1'bZ;
		119	`COL8 = 1'bZ;
		120	`COL9 = 1'bZ;
		121	`COL10 = 1'bZ;
		122	`COL11 = 1'bZ;
		123	`COL12 = 1'bZ;
		124	end
		125
		126	SWITCH_ROW1: begin
		127	`SWROW2 = 1'b0;
		128
		129	switch[1][1] = ~`COL1;
		130	switch[1][2] = ~`COL2;
		131	switch[1][3] = ~`COL3;
		132	switch[1][4] = ~`COL4;
		133	switch[1][5] = ~`COL5;
		134	switch[1][6] = ~`COL6;
		135	switch[1][7] = ~`COL7;
		136	switch[1][8] = ~`COL8;
		137	switch[1][9] = ~`COL9;
		138	switch[1][10] = ~`COL10;
		139	switch[1][11] = ~`COL11;
		140	switch[1][12] = ~`COL12;
		141	end
		142
		143	SWITCH_ROW2: begin
		144	`SWROW3 = 1'b0;
		145
		146	switch[2][1] = ~`COL1;
		147	switch[2][2] = ~`COL2;
		148	switch[2][3] = ~`COL3;
		149	switch[2][4] = ~`COL4;
		150	switch[2][5] = ~`COL5;
		151	switch[2][6] = ~`COL6;
		152	switch[2][7] = ~`COL7;
		153	switch[2][8] = ~`COL8;
		154	switch[2][9] = ~`COL9;
		155	switch[2][10] = ~`COL10;
		156	switch[2][11] = ~`COL11;
		157	switch[2][12] = ~`COL12;
		158	end
		159
		160	SWITCH_ROW3: begin
		161	switch[3][1] = ~`COL1;
		162	switch[3][2] = ~`COL2;
		163	switch[3][3] = ~`COL3;
		164	switch[3][4] = ~`COL4;
		165	switch[3][5] = ~`COL5;
		166	switch[3][6] = ~`COL6;
		167	switch[3][7] = ~`COL7;
		168	switch[3][8] = ~`COL8;
		169	switch[3][9] = ~`COL9;
		170	switch[3][10] = ~`COL10;
		171	switch[3][11] = ~`COL11;
		172	switch[3][12] = ~`COL12;
		173	end
		174	`endif
		175	endcase
		176
		177	if (state == state.last)
		178	state = state.first;
		179	else
		180	state = state.next;
		181	end
		182	end
		183
		184	endmodule


diff --git a/hdl/top.sv b/hdl/top.sv index 1d77216..abd6f30 100644 --- a/hdl/top.sv +++ b/hdl/top.sv
@@ -3,6 +3,10 @@
3	module top	3	module top
4	( input bit native_clk // verilator public	4	( input bit native_clk // verilator public
5	, input bit reset_n // verilator public	5	, input bit reset_n // verilator public
		6
		7	, inout wire [10:1] gpioa
		8	, inout wire [28:13] gpiob
		9	, inout wire [40:31] gpioc
6	);	10	);
7		11
8	bit clk;	12	bit clk;
@@ -18,9 +22,61 @@ clock
18	, .reset(reset)	22	, .reset(reset)
19	);	23	);
20		24
		25	bit slowclk;
		26	bit slowreset;
		27	clock
		28	#( .MULTIPLY_BY(1)
		29	, .DIVIDE_BY(5000)
		30	) slowpll
		31	( .native_clk(native_clk)
		32	, .reset_n(reset_n)
		33	, .target_clk(slowclk)
		34	, .reset(slowreset)
		35	);
		36
		37	bit [8:1][12:1] led;
		38	bit [3:1][12:1] switch;
		39
		40	panel fp
		41	( .clk(slowclk)
		42	, .reset(slowreset)
		43
		44	, .led(led)
		45	, .switch(switch)
		46
		47	, .gpioa(gpioa)
		48	, .gpiob(gpiob)
		49	, .gpioc(gpioc)
		50	);
		51
		52	assign led[1] = switch[1];
		53	assign led[2] = switch[2];
		54	assign led[3] = switch[3];
		55	assign led[4] = 0;
		56	assign led[5] = 0;
		57	assign led[6] = 0;
		58	assign led[7] = 0;
		59	assign led[8] = 0;
		60
		61	/*
		62	wire [7:0] debugchar;
		63	assign debugchar = "0" + {switch[1][1], switch[1][2], switch[3][1]};
		64
		65	jtag_uart debug
		66	( .clk(slowclk)
		67	, .reset(slowreset)
		68
		69	, .rx_ready(0)
		70	, .tx_valid(1)
		71	, .tx_data(debugchar)
		72	);
		73	*/
		74
		75	/*
21	core cpu	76	core cpu
22	( .clk(clk)	77	( .clk(clk)
23	, .reset(reset)	78	, .reset(reset)
24	);	79	);
		80	*/
25		81
26	endmodule	82	endmodule


diff --git a/tcl/init.tcl b/tcl/init.tcl index 3466f17..9f296f3 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl
@@ -6,13 +6,56 @@ set_global_assignment -name TOP_LEVEL_ENTITY top
6	set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005	6	set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
7	set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"	7	set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
8		8
9	proc pin {loc net} {	9	proc pin {net loc} {
10	set_location_assignment -to $net "PIN_$loc"	10	set_location_assignment -to $net "PIN_$loc"
11	set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net	11	set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
12	}	12	}
13		13
14	pin E1 native_clk	14	proc iopin {net loc} {
15	pin J15 reset_n	15	pin $net $loc
		16	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to $net
		17	}
		18
		19	pin native_clk E1
		20
		21	iopin reset_n J15
		22
		23	iopin gpioa[1] L13
		24	iopin gpioa[2] L16
		25	iopin gpioa[3] L15
		26	iopin gpioa[4] K16
		27	iopin gpioa[5] P16
		28	iopin gpioa[6] R16
		29	iopin gpioa[7] N16
		30	iopin gpioa[8] N15
		31	iopin gpioa[9] N14
		32	iopin gpioa[10] P15
		33	iopin gpiob[13] N8
		34	iopin gpiob[14] P8
		35	iopin gpiob[15] M8
		36	iopin gpiob[16] L8
		37	iopin gpiob[17] R7
		38	iopin gpiob[18] T7
		39	iopin gpiob[19] L7
		40	iopin gpiob[20] M7
		41	iopin gpiob[21] R6
		42	iopin gpiob[22] T6
		43	iopin gpiob[23] T2
		44	iopin gpiob[24] M6
		45	iopin gpiob[25] R5
		46	iopin gpiob[26] T5
		47	iopin gpiob[27] N5
		48	iopin gpiob[28] N6
		49	iopin gpioc[31] R4
		50	iopin gpioc[32] T4
		51	iopin gpioc[33] N3
		52	iopin gpioc[34] P3
		53	iopin gpioc[35] R3
		54	iopin gpioc[36] T3
		55	iopin gpioc[37] P6
		56	iopin gpioc[38] P2
		57	iopin gpioc[39] P1
		58	iopin gpioc[40] R1
16		59
17	# This is the clock for timing-driven synthesis, not timing analysis.	60	# This is the clock for timing-driven synthesis, not timing analysis.
18	# See clocks.sdf for the other clock.	61	# See clocks.sdf for the other clock.