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`include "util.svh"
module top
( input bit native_clk // verilator public
, input bit reset_n // verilator public
, inout wire [10:1] gpioa
, inout wire [28:13] gpiob
, inout wire [40:31] gpioc
);
bit clk;
bit reset;
clock
#( .MULTIPLY_BY(9)
, .DIVIDE_BY(10)
) pll
( .native_clk(native_clk)
, .reset_n(reset_n)
, .target_clk(clk)
, .reset(reset)
);
bit slowclk;
bit slowreset;
clock
#( .MULTIPLY_BY(1)
, .DIVIDE_BY(5000)
) slowpll
( .native_clk(native_clk)
, .reset_n(reset_n)
, .target_clk(slowclk)
, .reset(slowreset)
);
bit [8:1][12:1] led;
bit [3:1][12:1] switch;
panel fp
( .clk(slowclk)
, .reset(slowreset)
, .led(led)
, .switch(switch)
, .gpioa(gpioa)
, .gpiob(gpiob)
, .gpioc(gpioc)
);
assign led[1] = switch[1];
assign led[2] = switch[2];
assign led[3] = switch[3];
assign led[4] = 0;
assign led[5] = 0;
assign led[6] = 0;
assign led[7] = 0;
assign led[8] = 0;
/*
wire [7:0] debugchar;
assign debugchar = "0" + {switch[1][1], switch[1][2], switch[3][1]};
jtag_uart debug
( .clk(slowclk)
, .reset(slowreset)
, .rx_ready(0)
, .tx_valid(1)
, .tx_data(debugchar)
);
*/
/*
core cpu
( .clk(clk)
, .reset(reset)
);
*/
endmodule
|
