1 files changed, 22 insertions, 2 deletions

diff --git a/PLAN b/PLAN
index 2e32e77..40d9232 100644
--- a/PLAN
+++ b/PLAN
@@ -1,2 +1,22 @@
-Instrument simh to have deterministic input timing (stuffed input queue)
-Instrument simh to have diagnostic messages about interrupt sources and terminal/keyboard/interrupt enable flags
+[ ] External RAM
+    [ ] Decouple timing
+    [ ] Init memory on startup
+        [ ] Build Arduino interface and separate protocol for computer-based init
+        [ ] Fill FPGA ROMs with initial memory image and teach it to copy at reset
+        [ ] Hack a protocol on top of nios2-terminal's translation using expect
+[ ] Source code cleanup
+    [ ] Maybe switch to a standardized bus between modules (e.g. WISHBONE)
+    [ ] Maybe switch to a standardized package format (e.g. FuseSoC)
+[ ] Pipelined / out-of-order design?
+[ ] Better decoupling of front panel (built-time option)
+    [ ] Same for UART
+[ ] External serial UART
+[ ] External tape?
+[ ] External graphic display?
+[ ] Networking multiple PDP-8s in the same SOC
+[ ] Other ISA support
+    [ ] Z80 / 6502
+    [ ] PDP-11
+    [ ] 8086
+    [ ] Maybe a new ISA?
+[ ] Put the PDP-8 in the box