1 files changed, 15 insertions, 22 deletions

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index 2b5f334..096b1c9 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -18,13 +18,6 @@ module jtag_uart
     ,   input   bit [7:0]   tx_data
     );
 
-`input(rx_ready)
-`output(rx_valid)
-`output(rx_data)
-`output(tx_ready)
-`input(tx_valid)
-`input(tx_data)
-
 `ifdef SYNTHESIS
 
 alt_jtag_atlantic
@@ -35,12 +28,12 @@ alt_jtag_atlantic
     ) real_jtag
     (   .clk(clk)
     ,   .rst_n(!reset)
-    ,   .r_dat(tx_data_)
-    ,   .r_val(tx_valid_)
-    ,   .r_ena(tx_ready_)
-    ,   .t_dat(rx_data_)
-    ,   .t_dav(rx_ready_)
-    ,   .t_ena(rx_valid_)
+    ,   .r_dat(tx_data)
+    ,   .r_val(tx_valid)
+    ,   .r_ena(tx_ready)
+    ,   .t_dat(rx_data)
+    ,   .t_dav(rx_ready)
+    ,   .t_ena(rx_valid)
     );
 
 `else
@@ -55,34 +48,34 @@ bit [7:0] tx_b_data;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        rx_valid_ = 0;
-        tx_ready_ = 0;
+        rx_valid = 0;
+        tx_ready = 0;
         sim_rx_addr = 0;
         tx_b_valid = 0;
     end else begin
         automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
 
         // RX logic
-        if (rx_ready_) rx_valid_ = 0;
-        if (!rx_valid_ && (sim_rx_data != 0)) begin
+        if (`lag(rx_ready)) rx_valid = 0;
+        if (!rx_valid && (sim_rx_data != 0)) begin
 `ifdef JTAG_UART_LOCAL_ECHO
             $write("%s", sim_rx_data);
 `endif
-            rx_valid_ = 1;
-            rx_data_ = sim_rx_data;
+            rx_valid = 1;
+            rx_data = sim_rx_data;
             ++sim_rx_addr;
         end
 
         // TX logic
-        if (tx_ready_ && tx_valid_) begin
+        if (tx_ready && `lag(tx_valid)) begin
             tx_b_valid = 1;
-            tx_b_data = tx_data_;
+            tx_b_data = `lag(tx_data);
         end
         if (tx_b_valid) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
-        tx_ready_ = !tx_b_valid;
+        tx_ready = !tx_b_valid;
     end
 end