1 files changed, 16 insertions, 5 deletions

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index 096b1c9..ec39c37 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -38,6 +38,9 @@ alt_jtag_atlantic
 
 `else
 
+`define DELAY_BITS 16
+bit [`DELAY_BITS-1:0] delay;
+
 bit [7:0] sim_rx_rom [0:(1<<16)-1];
 initial $readmemh("mem/jtag_uart.hex", sim_rx_rom);
 
@@ -48,6 +51,7 @@ bit [7:0] tx_b_data;
 
 always_ff @(posedge clk) begin
     if (reset) begin
+        delay = {(`DELAY_BITS){1'b1}};
         rx_valid = 0;
         tx_ready = 0;
         sim_rx_addr = 0;
@@ -57,13 +61,19 @@ always_ff @(posedge clk) begin
 
         // RX logic
         if (`lag(rx_ready)) rx_valid = 0;
-        if (!rx_valid && (sim_rx_data != 0)) begin
+        if (delay == 0) begin
+            delay = {(`DELAY_BITS){1'b1}};
+            if (!rx_valid && (sim_rx_data != 8'hff)) begin
 `ifdef JTAG_UART_LOCAL_ECHO
-            $write("%s", sim_rx_data);
+                $write("%s", sim_rx_data);
+                $fflush();
 `endif
-            rx_valid = 1;
-            rx_data = sim_rx_data;
-            ++sim_rx_addr;
+                rx_valid = 1;
+                rx_data = sim_rx_data;
+                ++sim_rx_addr;
+            end
+        end else begin
+            --delay;
         end
 
         // TX logic
@@ -73,6 +83,7 @@ always_ff @(posedge clk) begin
         end
         if (tx_b_valid) begin
             $write("%s", tx_b_data);
+            $fflush();
             tx_b_valid = 0;
         end
         tx_ready = !tx_b_valid;