PLAN


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Turn on blinkenlights from the PDP core

Implement switch features:
    Start
    Load_Add
    Deposit
    Examine
    The DF* IF* and SR* data switches

Don't ignore 6000 and 6001

Add "interrupts enabled" flag
6000, 6001, 6002 should properly handle it
    6000 - skip next instruction if interrupts are enabled; disable interrupts (we should probably do this immediately)
    6001 - enable interrupts (after next instruction)
    6002 - disable interrupts (we should probably do this immediately)

Implement remaining TTY output instructions

Jules thinks clock is most likely interrupt source
    pdp8 source tries to map clock interrupts to "real time" - we might want to mangle that to make it deterministic

Sources of interrupts observed:
    PTR flag is set from loader, might be ignorable
    Memory management is poked from inside ISRs, might be ignorable (MMU should be optional)
    TTO ready for output interrupt - this looks like a very likely candidate
    TTI input ready interrupt - this looks like a very likely candidate
        Looks like these happen even when there is no input available - might be caused by the program itself doing something a little funny