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project_new noncpu -revision noncpu -overwrite
set_global_assignment -name DEVICE 10CL025YU256I7G
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
proc pin {net loc} {
set_location_assignment -to $net "PIN_$loc"
set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
}
proc iopin {net loc} {
pin $net $loc
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to $net
}
pin native_clk E1
iopin reset_n J15
iopin gpioa[1] L13
iopin gpioa[2] L16
iopin gpioa[3] L15
iopin gpioa[4] K16
iopin gpioa[5] P16
iopin gpioa[6] R16
iopin gpioa[7] N16
iopin gpioa[8] N15
iopin gpioa[9] N14
iopin gpioa[10] P15
iopin gpiob[13] N8
iopin gpiob[14] P8
iopin gpiob[15] M8
iopin gpiob[16] L8
iopin gpiob[17] R7
iopin gpiob[18] T7
iopin gpiob[19] L7
iopin gpiob[20] M7
iopin gpiob[21] R6
iopin gpiob[22] T6
iopin gpiob[23] T2
iopin gpiob[24] M6
iopin gpiob[25] R5
iopin gpiob[26] T5
iopin gpiob[27] N5
iopin gpiob[28] N6
iopin gpioc[31] R4
iopin gpioc[32] T4
iopin gpioc[33] N3
iopin gpioc[34] P3
iopin gpioc[35] R3
iopin gpioc[36] T3
iopin gpioc[37] P6
iopin gpioc[38] P2
iopin gpioc[39] P1
iopin gpioc[40] R1
# This is the clock for timing-driven synthesis, not timing analysis.
# See clocks.sdf for the other clock.
create_base_clock -fmax "45 MHz" clk
proc add_files {typ ext dir} {
foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] {
set_global_assignment -name "${typ}_FILE" $name
}
}
proc add_dir {dir} {
add_files CDF cdf $dir
add_files HEX hex $dir
add_files SDC sdc $dir
add_files VERILOG sv $dir
add_files VERILOG svh $dir
foreach subdir [glob -nocomplain -directory $dir -type d *] {
add_dir $subdir
}
}
add_dir .
project_close
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