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| author | Julian Blake Kongslie | 2022-02-16 14:44:01 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-16 14:44:01 -0800 |
| commit | 92420e248d4449a2aa61e92f05c0867912d48d56 (patch) | |
| tree | 889d0af684d648713cd1ae68b5b2c550d2b6dc7f /hdl/command_parser.sv | |
| parent | Complete rewrite to break out the separate state machines and fix timing (diff) | |
| download | simple-memory-controller-92420e248d4449a2aa61e92f05c0867912d48d56.tar.xz | |
Split into multiple files.
Diffstat (limited to 'hdl/command_parser.sv')
| -rw-r--r-- | hdl/command_parser.sv | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv new file mode 100644 index 0000000..d6775ad --- /dev/null +++ b/hdl/command_parser.sv | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | module command_parser | ||
| 2 | ( input bit clock | ||
| 3 | , input bit resetn | ||
| 4 | |||
| 5 | , output bit uart_ready | ||
| 6 | , input bit uart_valid | ||
| 7 | , input bit [7:0] uart_data | ||
| 8 | |||
| 9 | , input bit echo_ready | ||
| 10 | , output bit echo_valid | ||
| 11 | , output bit [7:0] echo_data | ||
| 12 | |||
| 13 | , input bit command_ready | ||
| 14 | , output bit command_valid | ||
| 15 | , output bit [23:0] command_address | ||
| 16 | , output bit command_write | ||
| 17 | , output bit [15:0] command_data | ||
| 18 | ); | ||
| 19 | |||
| 20 | bit input_byte_valid; | ||
| 21 | bit [7:0] input_byte; | ||
| 22 | |||
| 23 | enum | ||
| 24 | { READ_ADDRESS_OR_COMMAND | ||
| 25 | , READ_DATA_1 | ||
| 26 | , READ_DATA_2 | ||
| 27 | , READ_DATA_3 | ||
| 28 | , READ_DATA_4 | ||
| 29 | } state; | ||
| 30 | |||
| 31 | always @(posedge clock) begin | ||
| 32 | if (!resetn) begin | ||
| 33 | uart_ready = 0; | ||
| 34 | command_valid = 0; | ||
| 35 | command_address = 0; | ||
| 36 | command_write = 0; | ||
| 37 | command_data = 0; | ||
| 38 | input_byte_valid = 0; | ||
| 39 | input_byte = 0; | ||
| 40 | state = state.first; | ||
| 41 | end else begin | ||
| 42 | if (echo_ready) echo_valid = 0; | ||
| 43 | if (command_ready) command_valid = 0; | ||
| 44 | if (uart_ready && uart_valid) begin | ||
| 45 | echo_valid = 1; | ||
| 46 | echo_data = uart_data; | ||
| 47 | input_byte_valid = 1; | ||
| 48 | input_byte = uart_data; | ||
| 49 | end | ||
| 50 | |||
| 51 | if (!command_valid && input_byte_valid) begin | ||
| 52 | case (state) | ||
| 53 | |||
| 54 | READ_ADDRESS_OR_COMMAND: begin | ||
| 55 | if (input_byte >= "0" && input_byte <= "9") begin | ||
| 56 | command_address = command_address << 4; | ||
| 57 | command_address[3:0] = input_byte - "0"; | ||
| 58 | end else if (input_byte >= "a" && input_byte <= "f") begin | ||
| 59 | command_address = command_address << 4; | ||
| 60 | command_address[3:0] = input_byte - "a" + 10; | ||
| 61 | end else if (input_byte >= "A" && input_byte <= "F") begin | ||
| 62 | command_address = command_address << 4; | ||
| 63 | command_address[3:0] = input_byte - "A" + 10; | ||
| 64 | end else if (input_byte == "?") begin | ||
| 65 | command_valid = 1; | ||
| 66 | command_write = 0; | ||
| 67 | command_data = 0; | ||
| 68 | end else if (input_byte == "=") begin | ||
| 69 | command_write = 1; | ||
| 70 | command_data = 0; | ||
| 71 | state = READ_DATA_1; | ||
| 72 | end | ||
| 73 | end | ||
| 74 | |||
| 75 | READ_DATA_1, READ_DATA_2, READ_DATA_3, READ_DATA_4: begin | ||
| 76 | if (input_byte >= "0" && input_byte <= "9") begin | ||
| 77 | command_data = command_data << 4; | ||
| 78 | command_data[3:0] = input_byte - "0"; | ||
| 79 | state = state.next; | ||
| 80 | end else if (input_byte >= "a" && input_byte <= "f") begin | ||
| 81 | command_data = command_data << 4; | ||
| 82 | command_data[3:0] = input_byte - "a" + 10; | ||
| 83 | state = state.next; | ||
| 84 | end else if (input_byte >= "A" && input_byte <= "F") begin | ||
| 85 | command_data = command_data << 4; | ||
| 86 | command_data[3:0] = input_byte - "A" + 10; | ||
| 87 | state = state.next; | ||
| 88 | end else begin | ||
| 89 | state = state.first; | ||
| 90 | end | ||
| 91 | command_valid = state == state.first; | ||
| 92 | end | ||
| 93 | |||
| 94 | endcase | ||
| 95 | input_byte_valid = 0; | ||
| 96 | end | ||
| 97 | |||
| 98 | uart_ready = !echo_valid && !input_byte_valid; | ||
| 99 | end | ||
| 100 | end | ||
| 101 | |||
| 102 | endmodule | ||
