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| author | Julian Blake Kongslie | 2022-02-18 16:21:52 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-18 16:21:52 -0800 |
| commit | d2ecdbf5011f61228e0a3ed2441279bda551ed44 (patch) | |
| tree | 6dab75d8e8139f8151ad1d3ae830b92bce76cd43 /hdl | |
| parent | Explicitly unsigned states (in the vain hope of improving extraction) (diff) | |
| download | simple-memory-controller-d2ecdbf5011f61228e0a3ed2441279bda551ed44.tar.xz | |
Limit size of reset counter to something realistic.
Diffstat (limited to '')
| -rw-r--r-- | hdl/ram_controller.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv index 5950035..44d200b 100644 --- a/hdl/ram_controller.sv +++ b/hdl/ram_controller.sv | |||
| @@ -77,7 +77,7 @@ module ram_controller | |||
| 77 | , DATA_2 | 77 | , DATA_2 |
| 78 | } state; | 78 | } state; |
| 79 | 79 | ||
| 80 | int reset_counter; | 80 | bit [2:0] reset_counter; |
| 81 | 81 | ||
| 82 | always @(posedge clock) begin | 82 | always @(posedge clock) begin |
| 83 | if (!resetn || reset_counter != 0) begin | 83 | if (!resetn || reset_counter != 0) begin |